PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 18

• Manufacturer Part Number: PAC-POWR607-EV
• Description: MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of PAC-POWR607-EV

• Processor To Be Evaluated: ispPAC-POWR607
• Interface Type: JTAG
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.96 V
• Core Architecture: CPLD
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR607
• Primary Attributes: -
• Secondary Attributes: 4.5 ~ 9 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
ispPAC-POWR607 Data Sheet
accommodate the load voltage at the FET’s source, when the source pin of the FET is tied to the supply of the tar-
get board. When the HVOUT pin is sourcing current (charging a FET gate) the source current is 15µA. When the
driver is turned to the off state, the driver will sink current to ground, and this sink current is typically 2.5mA (1mA
min.) to quickly turn off the FET.
During initial power up and for short periods of time during programming, the HVOUTx pins will assume a high
impedance output configuration (Hi-Z). This occurs whether the pin is configured as a high voltage MOSFET driver
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or as an open drain output. It happens due to the period of uncertainty before the E
CMOS memory is resolved at
initial turn on and whenever being re-programmed. To insure any FETs controlled by ispPAC-POWR607 HVOUTx
pins are always off during these times, place a 10MΩ (min) resistor between each HVOUTx pin and ground. Since
this will subtract less than 1uA from the total drive capability of the HVOUT pin in FET driver mode, it will have a
negligible affect on its specified drive performance.
Software-Based Design Environment
Designers can configure the ispPAC-POWR607 using PAC-Designer, an easy to use, Microsoft Windows compati-
ble program. Circuit designs are entered graphically and then verified, all within the PAC-Designer environment.
Full device programming is supported using PC parallel port I/O operations and a download cable connected to the
serial programming interface pins of the ispPAC-POWR607. A library of configurations is included with basic solu-
tions and examples of advanced circuit techniques are available on the Lattice web site for downloading. In addi-
tion, comprehensive on-line and printed documentation is provided that covers all aspects of PAC-Designer
operation. The PAC-Designer schematic window, shown in Figure 4-15, provides access to all configurable ispPAC-
POWR607 elements via its graphical user interface. All analog input and output pins are represented. Static or non-
configurable pins such as power, ground, and the serial digital interface are omitted for clarity. Any element in the
schematic window can be accessed via mouse operations as well as menu commands. When completed, configu-
rations can be saved, simulated, and downloaded to devices.
Figure 4-15. PAC-Designer ispPAC-POWR607 Design Entry Screen
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