PAC-POWR607-EV Lattice, PAC-POWR607-EV Datasheet - Page 26

• Manufacturer Part Number: PAC-POWR607-EV
• Description: MCU, MPU & DSP Development Tools ispPAC POWR607 EVAL BRD
• Manufacturer: Lattice
• Series: ispPAC®r

Specifications of PAC-POWR607-EV

• Processor To Be Evaluated: ispPAC-POWR607
• Interface Type: JTAG
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Operating Supply Voltage: 3.96 V
• Core Architecture: CPLD
• Main Purpose: Power Management, Power Supply Supervisor/Tracker/Sequencer
• Embedded: Yes, Other
• Utilized Ic / Part: ispPAC-POWR607
• Primary Attributes: -
• Secondary Attributes: 4.5 ~ 9 V Supply
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
32-Pin QFN
Dimensions in millimeters
1. Use 32-pin QFNS package for all new designs. Refer to PCN #13A-08 for 32-pin QFN package discontinuance.
2X
PIN 1 ID
0.20
SEATING
PLANE
2.
NOTES: UNLESS OTHERWISE SPECIFIED
1.
4
5
3
C
3
0.20
2X
C
B
1
C
A
ALL DIMENSIONS ARE IN MILLIMETERS.
0
DIMENSIONS AND TOLERANCES
PER ANSI Y14.5M.
EXACT SHAPE AND SIZE OF THIS
FEATURE IS OPTIONAL.
DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.20 AND 0.25 mm FROM TERMINAL TIP.
APPLIES TO EXPOSED PORTION OF TERMINALS.
1
A
N
SIDE VIEW
TOP VIEW
5.00
4.75
2X
0.25
A3
4.75
A2
C
A1
A
A
5.00
B
2X
5
0.25
0.08
4-26
C
C
B
L
32X
SYMBOL
A1
A2
A3
D2
E2
A
b
L
e
0
BOTTOM VIEW
e
ispPAC-POWR607 Data Sheet
0.18
0.30
1.25
1.25
0.00
0.00
3.5
MIN.
D2
4X
b
-
-
4
0.10
0.20 REF
0.50 BSC
N
0.24
0.40
0.85
2.70
2.70
0.01
0.65
NOM.
M
-
C
A
1
LOCATED IN THIS AREA
PIN #1 ID FIDUCIAL
B
3
1.00
0.05
1.00
3.25
3.25
0.30
0.50
E2
MAX.
DIEPAD
(EXPOSED BACKSIDE)
12