P0071 Terasic Technologies Inc, P0071 Datasheet - Page 3
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P0071
Manufacturer Part Number
P0071
Description
TPAD MULTIMEDIADEVELOPMENT KIT
Manufacturer
Terasic Technologies Inc
Series
tPAD, Cyclone®IVr
Specifications of P0071
Main Purpose
Reference Design, Tablet
Embedded
Yes, FPGA / CPLD
Utilized Ic / Part
EP4CE115
Primary Attributes
8-Inch TFT LCD, LED Backlight
Secondary Attributes
5-Megapixel Digital Image Sensor
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Chapter 1
Introduction of the tPad
The tPad Embedded Evaluation Kit is a comprehensive design environment with everything
embedded developers need to create processing-based systems. The tPad delivers an integrated
platform that includes hardware, design tools, intellectual property (IP) and reference designs for
developing embedded software and hardware platform in a wide range of applications. The fully
integrated kit allows developers to rapidly customize their processor and IP to best suit their specific
application. The tPad features the DE2-115 development board targeting the Cyclone IV E FPGA,
as well as a LCD multimedia color touch panel and a 5-Megapixel digital image sensor module.
The tPad is preconfigured with an FPGA hardware reference design including several Ready-to-Run
demonstration applications stored on the provided SD-Card. Software developers can use these
reference designs as their platform to quickly architect, develop and build complex embedded
systems. By simply scrolling through the demo of your choice on the LCD multimedia color touch
panel, you can evaluate numerous processor system designs.
The all-in-one embedded solution offered on the tPad, in combination of the LCD touch panel and
digital image module, provide embedded developers the ideal platform for multimedia applications
with unparallel processing performance. Developers can benefit from the use of FPGA-based
embedded processing system such as mitigate design risk and obsolescence, design reuse, reducing
bill of material (BOM) costs by integrating powerful graphics engines within the FPGA, and lower
cost.
Figure 1-1
shows a photograph of the tPad.
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