MFRC52302HN1,151 NXP Semiconductors, MFRC52302HN1,151 Datasheet - Page 42

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MFRC52302HN1,151

Manufacturer Part Number
MFRC52302HN1,151
Description
IC READER 32-HVQFN
Manufacturer
NXP Semiconductors
Series
MIFARE®r
Datasheet

Specifications of MFRC52302HN1,151

Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935293911151
NXP Semiconductors
MFRC523
Product data sheet
COMPANY PUBLIC
9.2.1.10 FIFODataReg register
9.2.1.11 FIFOLevelReg register
Table 39.
Input and output of 64 byte FIFO buffer.
Table 40.
Table 41.
Indicates the number of bytes stored in the FIFO.
Table 42.
Bit
6
5 to 4
3
2 to 0
Bit
Symbol
Access
Bit
7 to 0
Bit
Symbol
Access
Symbol
I
reserved
MFCrypto1On
ModemState[2:0]
2
CForceHS
FlushBuffer
Symbol
FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. FIFO
Status2Reg register bit descriptions
FIFODataReg register (address 09h); reset value: xxh bit allocation
FIFODataReg register bit descriptions
FIFOLevelReg register (address 0Ah); reset value: 00h bit allocation
7
W
7
All information provided in this document is subject to legal disclaimers.
Rev. 3.7 — 8 November 2011
6
Description
buffer acts as parallel in/parallel out converter for all serial data stream
inputs and outputs
6
Value
1
0
-
-
-
000
001
010
011
100
101
110
115237
5
reserved
indicates that the MIFARE Crypto1 unit is switched on and
5
Description
I
all data communication with the card is encrypted; this bit is
cleared by software; can only be set to logic 1 by a
successful execution of the MFAuthent command only valid
in Read/Write mode for MIFARE standard cards
shows the state of the transmitter and receiver state
machines:
2
C-bus input filter settings:
the I
independent of the I
the I
idle
wait for the BitFramingReg register’s StartSend bit
TxWait: wait until RF field is present if the TModeReg
register’s TxWaitRF bit is set to logic 1. The minimum
time for TxWait is defined by the TxWaitReg register
transmitting
RxWait: wait until RF field is present if the TModeReg
register’s TxWaitRF bit is set to logic 1. The minimum
time for RxWait is defined by the RxWaitReg register
wait for data
receiving
2
2
C-bus input filter is set to the High-speed mode
C-bus input filter is set to the I
FIFOData[7:0]
4
4
…continued
D
FIFOLevel[6:0]
3
R
3
2
C-bus protocol
2
2
Contactless reader IC
MFRC523
2
C-bus protocol used
© NXP B.V. 2011. All rights reserved.
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