MFRC52302HN1,151 NXP Semiconductors, MFRC52302HN1,151 Datasheet - Page 40
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MFRC52302HN1,151
Manufacturer Part Number
MFRC52302HN1,151
Description
IC READER 32-HVQFN
Manufacturer
NXP Semiconductors
Series
MIFARE®r
Datasheet
1.MFRC52302HN1151.pdf
(98 pages)
Specifications of MFRC52302HN1,151
Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935293911151
NXP Semiconductors
MFRC523
Product data sheet
COMPANY PUBLIC
9.2.1.7 ErrorReg register
9.2.1.8 Status1Reg register
Error bit register showing the error status of the last command executed.
Table 34.
Table 35.
[1]
Contains status bits of the CRC, interrupt and FIFO buffer.
Table 36.
Bit
Symbol
Access
Bit Symbol
7
6
5
4
3
2
1
0
Bit
Symbol
Access
Command execution clears all error bits except the TempErr bit. Cannot be set by software.
WrErr
TempErr
reserved
BufferOvfl
CollErr
CRCErr
ParityErr
ProtocolErr 1
reserved CRCOk CRCReady
WrErr
ErrorReg register (address 06h); reset value: 00h bit allocation
ErrorReg register bit descriptions
Status1Reg register (address 07h); reset value: 21h bit allocation
R
7
[1]
7
-
All information provided in this document is subject to legal disclaimers.
Value Description
1
1
-
1
1
1
1
TempErr
R
6
Rev. 3.7 — 8 November 2011
R
6
data is written into the FIFO buffer by the host during the MFAuthent
command or if data is written into the FIFO buffer by the host during the
time between sending the last bit on the RF interface and receiving the
last bit on the RF interface
internal temperature sensor detects overheating, in which case the
antenna drivers are automatically switched off
reserved for future use
the host or a MFRC523’s internal state machine (e.g. receiver) tries to
write data to the FIFO buffer even though it is already full
a bit-collision is detected
cleared automatically at receiver start-up phase
only valid during the bitwise anticollision at 106 kBd
always set to logic 0 during communication protocols at 212 kBd,
424 kBd and 848 kBd
the RxModeReg register’s RxCRCEn bit is set and the CRC calculation
fails
automatically cleared to logic 0 during receiver start-up phase
parity check failed
automatically cleared during receiver start-up phase
only valid for ISO/IEC 14443 A/MIFARE communication at 106 kBd
set to logic 1 if the SOF is incorrect
automatically cleared during receiver start-up phase
bit is only valid for 106 kBd
during the MFAuthent command, the ProtocolErr bit is set to logic 1 if the
number of bytes received in one data stream is incorrect
reserved
115237
5
-
R
5
BufferOvfl
R
4
IRq
R
4
CollErr
TRunning reserved
R
3
R
3
CRCErr
R
2
2
-
Contactless reader IC
ParityErr
MFRC523
R
1
© NXP B.V. 2011. All rights reserved.
HiAlert
R
1
ProtocolErr
LoAlert
R
0
40 of 98
R
0