MFRC52302HN1,151 NXP Semiconductors, MFRC52302HN1,151 Datasheet - Page 30

• Manufacturer Part Number: MFRC52302HN1,151
• Description: IC READER 32-HVQFN
• Manufacturer: NXP Semiconductors
• Series: MIFARE®r

Specifications of MFRC52302HN1,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935293911151

NXP Semiconductors
MFRC523
Product data sheet
COMPANY PUBLIC
8.8.1 Hard power-down
8.8.2 Soft power-down mode
8.8 Power reduction modes
The timer can be started manually using the ControlReg register’s TStartNow bit and
stopped using the ControlReg register’s TStopNow bit.
The timer can also be activated automatically to meet any dedicated protocol
requirements, by setting the TModeReg register’s TAuto bit to logic 1.
The delay time of a timer stage is set by the reload value + 1. The total delay time (t
calculated using
or if the TPrescalEven bit is set, using
An example of calculating total delay time (t
TPrescaler value = 4095 and TReloadVal = 65535:
Example: To give a delay time of 25 s requires 339 clock cycles to be counted and a
TPrescaler value of 169. This configures the timer to count up to 65535 time-slots for
every 25 s period.
Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pins and
clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or
LOW level.
Soft power-down mode is entered immediately after the CommandReg register’s
PowerDown bit is set to logic 1. All internal current sinks are switched off, including the
oscillator buffer. However, the digital input buffers are not separated from the input pins
and keep their functionality. The digital output pins do not change their state.
During soft power-down, all register values, the FIFO buffer content and the configuration
keep their current contents.
After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down
mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately
clear it. It is automatically cleared by the MFRC523 when Soft power-down mode is
exited.
Remark: When the internal oscillator is used, time (t
become stable. This is because the internal oscillator is supplied by V
cycles will not be detected by the internal logic until V
the serial UART, to first send the value 55h to the MFRC523. The oscillator must be stable
t
t
39.59 s
d
d
=
=

---------------------------------------------------------------------------------------------------------

---------------------------------------------------------------------------------------------------------
TPrescaler
TPrescaler
=

---------------------------------------------------------------------- -
4095
All information provided in this document is subject to legal disclaimers.

Equation


2
13.56 MHz
13.56 MHz
13.56 MHz
+
2
2
Rev. 3.7 — 8 November 2011
+
+
1

1
2






5:
65535


TReloadVal
TReloadVal
115237
+
1

Equation
+
+
1
1
d


) is shown in
6:
osc
DDA
) is required for the oscillator to
is stable. It is recommended for
Equation
Contactless reader IC
7, where the
MFRC523
DDA
© NXP B.V. 2011. All rights reserved.
and any clock
30 of 98
d
) is
(5)
(6)
(7)