PN5120A0HN1/C2,151 NXP Semiconductors, PN5120A0HN1/C2,151 Datasheet - Page 65

• Manufacturer Part Number: PN5120A0HN1/C2,151
• Description: IC TRANSMISSION MOD 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN1/C2,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
111334
Product data sheet
10.2.1 General
An interface compatible to an SPI interface enables a high-speed serial communication
between the PN512 and a μ-Controller up to 5 Mbit in order to handle the requirements for
the NFCIP-1 communication. The implemented SPI compatible interface is according to a
standard SPI interface.
For timing specification refer to
The PN512 acts as a slave during the SPI communication. The SPI clock SCK has to be
generated by the master. Data communication from the master to the slave uses the Line
MOSI. Line MISO is used to send data back from the PN512 to the master.
On both lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI line
should be stable on rising edge of the clock line and can changed on falling edge. The
same is valid for the MISO line. Data is provided by the PN512 on falling edge and is
stable during rising edge.
Read data:
To read out data using the SPI compatible interface the following byte order has to be
used. It is possible to read out up to n-data bytes.
The first sent byte defines both, the mode itself and the address byte.
Table 140. Byte Order for MOSI and MISO
Remark: The most significant bit (MSB) has to be send first.
Fig 13. Connection to host controller with SPI
MOSI
MISO
SCK
MOSI
MISO
NSS
byte 0
adr 0
X
Rev. 3.4 — 8 September 2009
byte 1
data 0
adr 1
Section 24.8 “Timing for the SPI compatible
byte 2
data 1
adr 2
SCK
MOSI
MISO
NSS
……..
……..
to
PN512
Transmission Module
data n-1
byte n
adr n
© NXP B.V. 2010. All rights reserved.
PN512
interface”.
byte n+1
data n
00
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