PN5120A0HN1/C2,151 NXP Semiconductors, PN5120A0HN1/C2,151 Datasheet - Page 39

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PN5120A0HN1/C2,151

Manufacturer Part Number
PN5120A0HN1/C2,151
Description
IC TRANSMISSION MOD 32-HVQFN
Manufacturer
NXP Semiconductors
Datasheets

Specifications of PN5120A0HN1/C2,151

Rf Type
Read / Write
Frequency
13.56MHz
Features
ISO14443-A, ISO14443-B
Package / Case
32-VFQFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PN5120A0HN1/C2,151
Manufacturer:
NXP/恩智浦
Quantity:
20 000
NXP Semiconductors
111334
Product data sheet
8.2.2.15 TypeBReg
8.2.2.16 SerialSpeedReg
Table 65.
Table 66.
Selects the speed of the serial UART interface.
Table 67.
Table 68.
Bit
7
6
5
4
3
2
1 to 0
Bit
7 to 5
3 to 0
Access
Access
Rights
Rights
Symbol
RxSOFReq
RxEOFReq
-
EOFSOFWidth If this bit is set to logic 1, the SOF and EOF will have the maximum
NoTxSOF
NoTxEOF
TxEGT
Symbol
BR_T0
BR_T1
RxSOF
TypeBReg register (address 1Eh); reset value: 00h, 00000000b
Description of TypeBReg bits
SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b
Description of SerialSpeedReg bits
Req
r/w
r/w
7
7
RxEOF
BR_T0
Rev. 3.4 — 8 September 2009
Req
r/w
r/w
6
6
Description
Factor BR_T0 to adjust the transfer speed, for description see
10.3.2 “Selection of the transfer
Factor BR_T1 to adjust the transfer speed, for description see
10.3.2 “Selection of the transfer
Description
If this bit is set to logic 1, the SOF is required. A datastream starting
without SOF is ignored.
If this bit is cleared, a datastream with and without SOF is accepted.
The SOF will be removed and not written into the FIFO.
If this bit is set to logic 1, the EOF is required. A datastream ending
without EOF will generate a Protocol-Error. If this bit is cleared, a
datastream with and without EOF is accepted. The EOF will be
removed and not written into the FIFO.
Reserved for future use.
length defined in ISO/IEC 14443B.
If this bit is cleared, the SOF and EOF will have the minimum length
defined in ISO/IEC 14443B.
If this bit is set to logic 1, the generation of the SOF is suppressed.
If this bit is set to logic 1, the generation of the EOF is suppressed.
These bits define the length of the EGT.
Value Description
00 0 bit
01 1 bit
10 2 bits
11 3 bits
RFU
r/w
5
5
0
EOFSO
FWidth
r/w
r/w
4
4
NoTxSOF NoTxEOF
r/w
r/w
3
3
speeds”.
speeds”.
BR_T1
r/w
2
r/w
2
Transmission Module
© NXP B.V. 2010. All rights reserved.
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PN512
TxEGT
Section
Section
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