CDB5566 Cirrus Logic Inc, CDB5566 Datasheet - Page 28

Dev Bd For I/C 24-bit, Diff, 5kSPS, DAQ

CDB5566

Manufacturer Part Number
CDB5566
Description
Dev Bd For I/C 24-bit, Diff, 5kSPS, DAQ
Manufacturer
Cirrus Logic Inc
Type
A/Dr
Datasheets

Specifications of CDB5566

Number Of Adc's
1
Number Of Bits
24
Sampling Rate (per Second)
5k
Data Interface
SPI™
Inputs Per Adc
2 Differential
Input Range
0 ~ 4.096 V
Power (typ) @ Conditions
20mW @ 5kSPS
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
CS5566
Conversion Rate
5 KSPS
Resolution
24 bit
Maximum Clock Frequency
8 MHz
Interface Type
SPI
Supply Voltage (max)
3.3 V
Supply Voltage (min)
- 2.5 V
Product
Data Conversion Development Tools
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
CS5566
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
598-1557
CDB-5566
3/25/08
CS5566
SCLK – Serial Clock Input/Output, Pin 23
The SMODE pin determines whether the SCLK signal is an input or an output signal. SCLK
determines the rate at which data is clocked out of the SDO pin. If the converter is in SSC
mode, the SCLK frequency will be determined by the master clock frequency of the converter
(either MCLK or the internal oscillator). In SEC mode, the user determines the SCLK frequency.
If SMODE = VL (SSC Mode), SCLK will be in a high-impedance state when CS is high.
RDY – Ready, Pin 24
If CONV is low the converter will immediately start a conversion and RDY will remain high until
the conversion is completed. At the end of any conversion RDY falls to indicate that a conver-
sion word has been placed into the serial port. RDY will return high after all data bits are shifted
out of the serial port or two master clock cycles before new data becomes available if the CS pin
is inactive (high); or two master clock cycles before new data becomes available if the user
holds CS low but has not started reading the data from the converter when in SEC mode.
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DS806PP1

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