IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 7

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Figure 1–1. QDRII SRAM Controller System-Level Diagram
Notes to
(1)
(2)
Altera Corporation
November 2009
Optional, for Stratix II devices only.
Non-DQS mode only.
or Fail
Clock
Figure
Pass
1–1:
Example Design
Example
Fedback
System
DLL ( 1 )
PLL ( 2 )
Driver
Clock
PLL
The IP Toolbench-generated example design instantiates a phase-locked
loop (PLL), an optional DLL (for Stratix II devices only), an example
driver, and your QDRII SRAM Controller custom variation. The example
design is a fully-functional example design that can be simulated,
synthesized, and used in hardware. The example driver is a self-test
module that issues read and write commands to the controller and checks
the read data to produce the pass/fail and test complete signals.
You can replace the QDRII SRAM controller encrypted control logic in
the example design with your own custom logic, which allows you to use
the Altera clear-text resynchronization and pipeline logic and datapath
with your own control logic.
OpenCore Plus Evaluation
With Altera’s free OpenCore Plus evaluation feature, you can perform
the following actions:
Interface
Local
MegaCore Version 9.1
QDRII SRAM Controller
Resynchronization
QDRII SRAM Controller MegaCore Function User Guide
& Pipeline Logic
Control Logic
(Encrypted)
(Clear Text)
(Clear Text)
Datapath
Interface
About This MegaCore Function
SRAM
QDRII
QDRII SRAM
1–3