IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 27

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Altera Corporation
November 2009
<device name>_ver
auk_qdrii_lib
Table 2–5. Files to Compile—Verilog HDL Gate-Level Simulations
Library
f
<QUARTUS ROOTDIR>/eda/sim_lib/<device name>_atoms.v
<project directory>/simulation/<simulator name>/<toplevel_name>.vo
<project directory>/testbench/<project name>_tb.v
1.
2.
3.
4.
5.
Simulating in Third-Party Simulation Tools Using NativeLink
You can perform a simulation in a third-party simulation tool from within
the Quartus II software, using NativeLink.
For more information on NativeLink, refer to the Simulating Altera IP
Using NativeLink chapter in volume 3 of the Quartus II Handbook.
To set up simulation in the Quartus II software using NativeLink, follow
these steps:
1.
2.
Create a directory in the <project directory>\testbench directory.
Launch your simulation tool inside this directory and create the
following libraries:
●
●
Copy the <project directory>/simulation/<simulator name>_v.sdo file
into the compilation directory.
Compile the files in
Set the Tcl variable gRTL_DELAYS to 0, which tells the testbench not
to use the insert extra delays in the system, because these are
applied inside the gate level model. Configure your simulator to use
transport delays, a timestep of picoseconds, and to include the
auk_qdrii_lib and <device name>_ver library.
Create a custom variation with an IP functional simulation model.
Obtain and copy a memory model to a suitable location, for
example, the testbench directory.
1
<device name>_ver
auk_qdrii_lib
MegaCore Version 9.1
Before running the simulation you may also need to edit the
testbench to match the chosen memory model.
QDRII SRAM Controller MegaCore Function User Guide
Table 2–5
Filename
into the appropriate library.
Getting Started
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