IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 22

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Simulate the Example Design
2–12
QDRII SRAM Controller MegaCore Function User Guide
6.
Simulating With Other Simulators
The IP Toollbench-generated Tcl script is for the ModelSim simulator
only. If you prefer to use a different simulation tool, follow these
instructions. You can also use the generated script as a guide. You also
need to download and compile an appropriate memory model.
1
VHDL IP Functional Simulations
For VHDL simulations with IP functional simulation models, follow
these steps:
1.
2.
For a gate-level timing simulation (VHDL or Verilog HDL
ModelSim output from the Quartus II software), type the following
commands:
set use_gate_model 1
source <variation name>_vsim.tcl
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Create a directory in the <project directory>\testbench directory.
Launch your simulation tool inside this directory and create the
following libraries:
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The following variables apply in this section:
<QUARTUS ROOTDIR> is the Quartus II installation directory
<simulator name> is the name of your simulation tool
<device name> is the Altera device family name
<project name> is the name of your Quartus II top-level entity or
module.
<MegaCore install directory> is the QDRII SRAM Controller
installation directory
altera_mf
lpm
sgate
<device name>
auk_qdrii_lib
MegaCore Version 9.1
r
r
Altera Corporation
November 2009