IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 37
IPR-SRAM/QDRII
Manufacturer Part Number
IPR-SRAM/QDRII
Description
IP CORE Renewal Of IP-SRAM/QDRII
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-SRAM/QDRII
Software Application
IP CORE, Memory Controllers, SDRAM
Supported Families
HardCopy II, Stratix
Features
Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
Core Architecture
FPGA
Core Sub-architecture
HardCopy, Stratix
Rohs Compliant
NA
Function
QDRII SRAM Controller
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Altera Corporation
November 2009
When this initialization time has elapsed, the training group module
monitors the data coming back and checks for its validity.
When the training group module detects a pattern, it checks to see if it is
too early, too late, or on time. If the pattern is too early, the pointer moves
by one; too late, the pointer moves by one in the other direction. The
training group module retrains until the pointer is correct.
The RAM size ensures there is minimal latency, but there is enough slack
to compensate for the training pattern realignment.
Datapath
Figure 3–4 on page 3–6
MegaCore Version 9.1
QDRII SRAM Controller MegaCore Function User Guide
shows the datapath block diagram.
Functional Description
3–5
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