IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 29

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Compile the
Example Design
Altera Corporation
November 2009
f
To edit the example PLL, follow these steps:
1.
2.
3.
4.
5.
For more information on the altpll megafunction, refer to the
Quartus II Help or click Documentation in the altpll MegaWizard
Plug-In.
Before the Quartus II software compiles the example design it runs the IP
Toolbench-generated Tcl constraints script, auto_add_constraints.tcl.
The auto_add_qdrii_constraints.tcl script calls the
add_constraints_for_<variation name>.tcl script for each variation in your
design. The add_constraints_for_<variation name>.tcl script checks for
any previously added constraints, removes them, and then adds
constraints for that variation.
The constraints script analyzes and elaborates your design, to
automatically extract the hierarchy to your variation. To prevent the
constraints script analyzing and elaborating your design, turn on Enable
hierarchy control in the wizard, and enter the correct hierarchy path to
your data path (refer to step
When the constraints script runs, it creates another script,
remove_constraints_for_<variation name>.tcl, which you can use to
remove the constraints from your design.
To compile the example instance, follow these steps:
1.
Choose MegaWizard Plug-In Manager (Tools menu).
Select Edit an existing custom megafunction variation and click
Next.
In your Quartus II project directory, for VHDL choose
qdrii_pll_<device name>.vhd; for Verilog HDL choose
qdrii_pll_<device name>.v.
Click Next.
Edit the PLL parameters in the altpll MegaWizard Plug-In.
Optional. Enable TimeQuest Timing Analyzer.
a.
On the Assignments menu click Settings, expand Timing
Analysis Settings, and select Use TimeQuest Timing
Analyzer.
MegaCore Version 9.1
QDRII SRAM Controller MegaCore Function User Guide
13
on
page
2–6).
Getting Started
2–19