IPR-SRAM/QDRII Altera, IPR-SRAM/QDRII Datasheet - Page 33

• Manufacturer Part Number: IPR-SRAM/QDRII
• Description: IP CORE Renewal Of IP-SRAM/QDRII
• Manufacturer: Altera
• Type: MegaCorer

Specifications of IPR-SRAM/QDRII

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: HardCopy II, Stratix
• Features: Automatic Concatenation Of Consecutive Reads And Writes, Easy-to-Use IP Toolbench Interface
• Core Architecture: FPGA
• Core Sub-architecture: HardCopy, Stratix
• Rohs Compliant: NA
• Function: QDRII SRAM Controller
• License: Renewal License
• Lead Free Status / RoHS Status: na
• Lead Free Status / RoHS Status: na

Block
Description
Figure 3–1. QDRII SRAM Controller Block Diagram
Notes to
(1)
Altera Corporation
November 2009
avl_wait_request_wr
avl_wait_request_rd
avl_chipselect_wr
avl_chipselect_rd
avl_datavalid_rd
You can edit the qdrii_ prefix.
avl_byteen_wr
avl_byteen_rd
dll_delay_ctrl
avl_addr_wr
avl_data_wr
avl_addr_rd
avl_data_rd
resynch_clk
Figure
avl_clk_wr
avl_resetn
avl_write
avl_read
avl_clk
3–1:
Figure 3–1
MegaCore function.
The QDRII SRAM Controller comprises the following three parts:
■
■
■
The control logic gets read and write requests from the Avalon
interface and turn them into QDRII SRAM read and write requests,
with the correct timing and concatenating consecutive addresses
where applicable.
The resynchronization and pipeline logic provides the
resynchronization system, the training block, and the optional
pipeline logic.
The datapath contains all the I/O and the clock generation.
(Encrypted)
Control
Logic
shows a block diagram of the QDR SRAM controller
MegaCore Version 9.1
QDRII SRAM Controller
(1)
3. Functional Description
Resynchronization
& Pipeline Logic
(Clear Text)
(Clear Text)
Datapath
qdrii_a
qdrii_bwsn
qdrii_cq
qdrii_cqn
qdrii_d
qdrii_k
qdrii_kn
qdrii_q
qdrii_rpsn
qdrii_wpns
®
3–1