HCTL-2017 Avago Technologies US Inc., HCTL-2017 Datasheet - Page 8

• Manufacturer Part Number: HCTL-2017
• Description: Quadrature Decoder IC,16bit,PDIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-2017

• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 16-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-2010

Quadrature Decoder
The quadrature decoder decodes the incoming filtered
signals into count information. This circuitry multiplies
the resolution of the input signals by a factor of four
(4X decoding).
The quadrature decoder samples the outputs of the
CHA and CHB filters. Based on the past binary state of
the two signals and the present state, it outputs a count
signal and a direction signal to the integral position
counter.
Figure 9 shows the quadrature states of Channel A and
Channel B signals. The 4x decoder will output a count
signal for every state transition (count up and count
down). Figure 9 shows the valid state transitions for 4x
decoder. The 4x decoder will output a count signal at
respective state transition, depending on the counting
direction. Channel A leading channel B results in
counting up. Channel B leading channel A results in
counting down. Illegal state transitions, caused by faulty
encoders or noise severe enough to pass through the
filter, will produce an erroneous count.
Figure 9. 4x Decoder Mode
state
8
clk
chB
CHA
1
1
0
0
chA
1
1
CHB
0
0
Tes
1
4
Te
1
STATE
2
3
4
Valid State
Transitions
2
Telp
count up
1
3
(Count Up & Count Down)
Pulse
Pulse
Pulse
Pulse
4X Decoder
3
2
count
down
4
Design Considerations
The designer should be aware that the operation of the
digital filter places a timing constraint on the
relationship between incoming quadrature signals and
the external clock. Figure 8 shows the timing waveform
with an incremental encoder input. Since an input has
to be stable for three rising clock edges, the encoder
pulse width (t
three clock periods (3t
asynchronous input will be stable during three
consecutive rising clock edges. A realistic design also
has to take into account finite rise time of the
waveforms, asymmetry of the waveforms, and noise. In
the presence of large amounts of noise, t
much greater than 3t
the consecutive level sampling by the three-bit delay
filter. It should be noted that a change on the inputs
that is qualified by the filter will internally propagate in
a maximum of seven clock periods.
The quadrature decoder circuitry imposes a second
timing constraint between the external clock and the
input signals. There must be at least one clock period
between consecutive quadrature states. As shown in
Figure 8, a quadrature state is defined by consecutive
edges on both channels. Therefore, t
period) > t
from the nominal 90 degree phasing of input signals to
guarantee that t
Position Counter
This section consists of a 16-bit binary up/down counter
which counts on rising clock edges as explained in the
Quadrature Decoder Section. All 16-bit of data are
passed to the position data latch. The system can use
this count data in several ways:
A. System total range is d ≤ 16 bits, so the count
B. The system is cyclic with ≤ 16 bits of count per cycle.
C. System count is > 8 or 16 bits, so the count data is
D. The system count is >16 bits so the HCTL-2021/2017
represents "absolute" position.
RSTN (or CHI) is used to reset the counter every cycle
and the system uses the data to interpolate within
the cycle.
used as a relative or incremental position input for a
system software computation of absolute position.
In this case counter rollover occurs. In order to
prevent loss of position information, the processor
must read the outputs of the IC before the count
increments one-half of the maximum count
capability. Two's-complement arithmetic is normally
used to compute position from these periodic
position updates.
can be cascaded with other standard counter ICs to
give absolute position.
CLK
. The designer must account for deviations
E
ES
- low or high) has to be greater than
> t
CLK
CLK
CLK
.
to allow for the interruption of
). This guarantees that the
ES
(encoder state
E
should be