HCTL-2017 Avago Technologies US Inc., HCTL-2017 Datasheet - Page 4

• Manufacturer Part Number: HCTL-2017
• Description: Quadrature Decoder IC,16bit,PDIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-2017

• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 16-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-2010

Functional Pin Description
Table 4. Functional Pin Descriptions
4
CLK
CHA
CHB
RST
OE
CNT
U/D
CNT
D0
D1
D2
D3
D4
D5
D6
D7
NC
Symbol
V
V
SEL
DD
SS
DCDR
CAS
16
NA
NA
NA
1
15
14
13
12
11
10
NA
8
2
7
6
5
4
3
9
HCTL-2017 HCTL-2021
Pin
20
10
2
9
8
7
4
16
5
15
1
19
18
17
14
13
12
11
6
3
Description
Power Supply
Ground
CLK is a Schmitt-trigger input for the external clock signal.
CHA and CHB are Schmitt-trigger inputs that accept the outputs from a
latch is enabled into the 8-bit tri-state output buffer. As in OE/ above, SEL
is counting up or down and is intended to be used with the CNT
CNT
present before the rising edge of the CNT
internal counter overflows or underflows. The rising edge on this waveform
may be used to trigger an external counter.
bytes. The High byte is read first followed by the Low bytes.
Not connected - this pin should be left floating.
quadrature-encoded source, such as incremental optical shaft encoder. Two
channels, A and B, nominally 90 degrees out of phase, are required.
This active low Schmitt-trigger input clears the internal position counter
and the position latch. It also resets the inhibit logic. RST is asynchronous
This CMOS active low input enables the tri-state output buffers. The OE/
and SEL inputs are sampled by the internal inhibit logic on the falling edge
of the clock to control the loading of the internal position data latch.
These CMOS inputs directly controls which data byte from the position
also control the internal inhibit logic.
A pulse is presented on this LSTTL-compatible output when the quadrature
decoder has detected a state transition. CNT
This LSTTL-compatible output allows the user to determine whether the IC
A pulse is presented on this LSTTL-compatible output when the HCTL-2021
These LSTTL-compatible tri-state outputs form an 8-bit output ports through
with respect to any other input signals.
which the contents of the 16-bit position latch may be read in 2 sequential
CAS
1
SEL
0
outputs. The proper signal U (high level) or D/ (low level) will be
BYTE SELECTED
High
Low
DCDR
and CNT
CAS
outputs.
DCDR
and