HCTL-2017 Avago Technologies US Inc., HCTL-2017 Datasheet - Page 11

• Manufacturer Part Number: HCTL-2017
• Description: Quadrature Decoder IC,16bit,PDIP
• Manufacturer: Avago Technologies US Inc.

Specifications of HCTL-2017

• Applications: Encoder to Microprocessor
• Interface: 8-Bit Tristate
• Voltage - Supply: 4.5 V ~ 5.5 V
• Package / Case: 16-DIP (0.300", 7.62mm)
• Mounting Type: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 516-2010

General Interfacing
The 16-bit latch and inhibit logic allows access to 16
bits of count with an 8-bit bus. When only 8-bits of
count are required, a simple 8-bit (1-byte) mode is
available by holding SEL high continuously. This
disables the inhibit logic. OE provides control of the tri-
state bus, and read timing is shown in Figure 2 and 3.
For proper operation of the inhibit logic during a two-
byte read, OE and SEL must be synchronous with CLK
due to the falling edge sampling of OE and SEL.
The internal inhibit logic on the HCTL-2021/2017
inhibits the transfer of data from the counter to the
position data latch during the time that the latch
outputs are being read. The inhibit logic allows the
microprocessor / microcontroller to first read the high
order 4 or 8 bits from the latch and then read the low
order 8 bits from the latch. Meanwhile, the counter can
continue to keep track of the quadrature states from
the CHA and CHB input signals.
Figure 11 shows the simplified inhibit logic circuit. The
operation of the circuitry is illustrated in the read timing
shown in Figure 13.
Figure 13. Typical Interface Timing
11
Actions
1. On the rising edge of the clock, counter data is
2. When OE goes low, the outputs of the multiplexer
3. When the IC detects a low on OE and SEL during a
4. When SEL goes high, the data outputs change from
5. The first of two reset conditions for the inhibit logic
6. When OE goes high, the data lines change to a high
7. The IC detects a logic high on OE during a falling
transferred to the position data latch, provided the
inhibit signal is low.
are enabled onto the data lines. If SEL is low, then
the high order data bytes are enabled onto the data
lines. If SEL is high, then the low order data bytes
are enabled onto the data lines.
falling clock edge, the internal inhibit signal is
activated. This blocks new data from being
transferred from the counter to the position data
latch.
the high byte to the low byte.
is met when the IC detects a logic high on SEL and a
logic low on OE during a falling clock edge.
impedance state.
clock edge. This satisfies the second reset condition
for the inhibit logic.