HCTL-2032-SC Avago Technologies US Inc., HCTL-2032-SC Datasheet
HCTL-2032-SC
Specifications of HCTL-2032-SC
HCTL-2032-SC
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HCTL-2032-SC Summary of contents
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... Operation is specified for a tem- perature range from -40 to +100°C at clock frequencies up to 33MHz. The HCTL-2032 and HCTL-2032-SC have dual-axis capa- bility and index channel support. Both devices can be programmed as 4x/2x/1x count mode. The HCTL-2032 and HCTL2032-SC also provides quadrature decoder out- put signals and cascade signals for use with many stan- dard computer ICs ...
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... Mhz clock operation. HCTL-03-SC All features of HCTL-03. HCTL-0 Most of the HCTL-03 features. The device supports single axis, and no decoder out- put and cascade signals. The programmable count mode is set to 4x internally. PINOUT A VDD X/Y ...
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... HCTL - 2032 - SC 3) HCTL - 2022 3 ...
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... HCTL-2032 –SCT (Tape and Reel Version of HCTL-2032-SC) Notes Sprocket hole pitch cumulative tolerance 0.2 2. Camber in compliance with EIA 481 3. Pocket position relative to sprocket hole measured as true position of pocket, not pocket hole 4. All dimensions ...
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Operating Characteristics Table 1. Absolute Maximum Ratings (All voltages below are referenced to V Parameter DC Supply Voltage Input Voltage Storage Temperature [1] Operating Temperature Table 2. Recommended Operating Conditions Parameter DC Supply Voltage [1] Ambient Temperature Table 3. DC ...
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... Functional Pin Description Table 4. Functional Pin Descriptions Pin HCTL 2032/ HCTL Symbol 2032-SC 2022 Description Power Supply Ground SS CLK 5 3 CLK is a Schmitt-trigger input for the external clock signal. CHA 15 10 CHA X from a quadrature-encoded source, such as incremental optical shaft encoder. Two ...
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... CNTCAS pulse is presented on this LSTTL-compatible output when the HCTL-2032 / 2032 internal counter overflows or underflows. The rising edge on this waveform may CNTCAS used to trigger an external counter. Y TEST 23 16 This pin is used for internal testing. Tied it to ground or leave it floating for normal operation. ...
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Switching Characteristics Table 5. Switching Characteristics Max/Min specifications ± 5 Symbol Description t Clock Period CLK t Pulse width, clock high CHH 3 t Delay time, rising edge of clock to valid, ...
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CLK CLK OLD OLD D0-D7 D0-D7 Figure 1. Reset Waveform DATA DATA tDCD tDCD CLK CLK OLD OLD D0-D7 D0-D7 DATA DATA tDCD tDCD Figure 2. Waveforms for Positive Clock Edge Related Delays OE tODE HIGH - Z NOT STABLE ...
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CLK t UDDX / t UDDY U/DX U/DY CNTDECX CNTCASX CNTDECY CNTCASY t UDXS / t UDYS Figure 5. Decoder, Casade Output Timing CLK t XNYS XNY D0-D7 D0-D7 (1st-Axis Figure 6. Output Data from 1 -axis and ...
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CLK CHA CHB D0-D7 H'FFFFFFFF CNTDEC CNTCAS Figure 8. Quadrature decoder for 1 st -axis -axis (2x count mode) CLK CHA CHB D0-D7 H'FFFFFFFF CNTDEC CNTCAS st nd Figure 9. Quadrature decoder for 1 -axis/ 2 -axis (1x ...
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... Operation A block diagram of the HCTL-20XX-XX family is shown in Figure 10. The operation of each major function is de- scribed in the following sections. CLK Digital Filter CHAX CHAX filtered CHBX CHBX filtered CHAY CHAY filtered CHBY CHBY filtered CHIX CHIX filtered CHIY CHIY filtered RSTX RSTY ...
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Digital Noise Filter The digital noise filter section is responsible for rejecting noise on the incoming quadrature signals. The input sec- tion uses two techniques to implement improved noise rejection. Schmitt-trigger inputs and a three-clock-cycle delay filter combine to reject ...
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CLK CLK CHA CHB Noise Spike CHI CHA filtered CHB filtered CHI filtered Figure 12. Signal Propagation through Digital Noise Filter Quadrature Decoder The quadrature decoder decodes the incoming filtered signals into count information. ...
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... IC before the count increments one-half of the maximum count capability. Two’s- complement arithmetic is normally used to compute position from these periodic position updates. D. The system count is >32 bits so the HCTL-2032 / 2032- SC can be cascaded with other standard counter ICs to give absolute position. 1x ...
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... The SEL1, SEL2 and OE signals determine which byte is output and whether or not the output bus is in the high-Z state. In the HCTL- 20XX-XX, the data latch is 32 bit wide. Step ...
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... For example, suppose the HCTL-2032 / 2032-SC count is at FFFFFFFFh and an external counter is at F0h, with the count going up. A count occurring in the HCTL-2032 / 2032-SC will cause the counter to roll over and a cascade pulse will be generated. A read starting on this clock cy- cle will show FFFFFFFFh from the HCTL-2032 / 2032-SC ...
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... Interfacing the HCTL-2032 to an Atmel AVR 90S8535 The circuit shown in Figure 17 shows the connections be- tween an HCTL-2032 and an Atmel AVR controller. Data lines D0-D7 are connected to the Atmel AVR bus port. The 8 MHz oscillators clock the Atmel AVR, whereas the external 33 MHz oscillators clock the HCTL-2032. Figure 18 illustrates the program that interfaces with an Atmel AVR 90S8535 ...
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... Result = Result + Temp Mult = Mult * 256 Temp = Result_hi * Mult Result = Result + Temp ‘ Result = 32-bits Count Data ‘ Loop Figure 18. Typical Program for Reading HCTL-2032 with Atmel AVR 9 ‘Select X-axis ‘Disable OE ‘SEL1=0 (MSB) ‘SEL2=1 (MSB) ‘Enable OE ‘Get MSB ‘SEL1=1 (2nd Byte) ‘ ...
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... Lo_old = Pina Lo_new = Pina If Lo_new = Lo_old Then Result_lo = Lo_new Return Else Goto Get_lo End If Figure 18 Cont. Typical Program for Reading HCTL-2032 with Atmel AVR 0 ‘Get current data ‘Get 2nd Data ‘Get stable data ‘Get current data ‘Get 2nd Data ‘Get stable data ‘ ...
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... Actions 1. At first, Port B4, B5, and B6 are setup for 4X encoding and X/Y axis selection. 2. The HCTL-2032 detects that OE/ are low on the next falling edge of the CLK and asserts the internal inhibit signal. Data can be read without regard for the phase of the CLK. ...