HCTL-2017 Avago Technologies US Inc., HCTL-2017 Datasheet
HCTL-2017
Specifications of HCTL-2017
Available stocks
Related parts for HCTL-2017
HCTL-2017 Summary of contents
Page 1
... HCTL-2017 and HCTL-2021 Quadrature Decoder/Counter Interface ICs Data Sheet Description The HCTL-2021/2017 is CMOS ICs that performs the quadrature decoder, counter, and bus interface function. The HCTL-2021/2017 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution ...
Page 2
... VSS D7 9 PINOUT A Package Dimensions with Tolerances Length (L) HCTL-2017 22.86 ± 0.5 mm HCTL-2021 27.94 ± 0.5 mm (dimension in mm) HCTL-2021 SHOWN 2 Soldering and Mounting Considerations 1 D0 VDD 20 2 CLK recommended to use manual soldering for HCTL- 2021/2017 launch pad devices due to the characteristics ...
Page 3
Operating Characteristics Table 1. Absolute Maximum Ratings (All voltages below are referenced to VSS) Parameter DC Supply Voltage Input Voltage Storage Temperature Operating Temperature [1] Table 2. Recommended Operating Conditions Parameter Symbol DC Supply Voltage V Ambient Temperature [1] T ...
Page 4
... Functional Pin Description Table 4. Functional Pin Descriptions Pin Symbol HCTL-2017 HCTL-2021 CLK 2 2 CHA 7 9 CHB 6 8 RST SEL 3 3 CNT NA 16 DCDR U CNT NA 15 CAS Description Power Supply Ground CLK is a Schmitt-trigger input for the external clock signal. CHA and CHB are Schmitt-trigger inputs that accept the outputs from a quadrature-encoded source, such as incremental optical shaft encoder ...
Page 5
Switching Characteristics Table 5. Switching Characteristics Max/Min specifications at VDD = 5 -40 to +85 OC Symbol Description 1 t Clock Period CLK 2 t Pulse width, clock high CHH 3 t ...
Page 6
... Figure 4. Bus Control Timing Figure 5. Decoder, Cascade Output Timing Operation A block diagram of the HCTL-20xx family is shown in Figure 6. The operation of each major function is described in the following sections. Figure 6. Simplified Logic Diagram 6 ...
Page 7
Digital Noise Filter The digital noise filter section is responsible for rejecting noise on the incoming quadrature signals. The input section uses two techniques to implement improved noise rejection. Schmitt-trigger inputs and a three-clock- cycle delay filter combine to reject ...
Page 8
... IC before the count increments one-half of the maximum count capability. Two's-complement arithmetic is normally used to compute position from these periodic position updates. D. The system count is >16 bits so the HCTL-2021/2017 can be cascaded with other standard counter ICs to give absolute position. - low or high) has to be greater than E ) ...
Page 9
... Quadrature Decoder Output The quadrature decoder output section consists of count and up/down outputs derived from the 4x decoder mode of the HCTL-2021/2017. When the decoder has detected a count, a pulse, one-half clock cycle long, will be output on the CNT output will occur during the clock cycle in which the internal counter is updated ...
Page 10
... For example, suppose the HCTL-2021/2017 count is at FFFFh and an external counter is at F0h, with the count going up. A count occurring in the HCTL-2021/2017 will cause the counter to roll over and a cascade pulse will be generated. A read starting on this clock cycle will show FFFFh from the HCTL-2021/2017. The external ...
Page 11
... For proper operation of the inhibit logic during a two- byte read, OE and SEL must be synchronous with CLK due to the falling edge sampling of OE and SEL. The internal inhibit logic on the HCTL-2021/2017 inhibits the transfer of data from the counter to the position data latch during the time that the latch outputs are being read ...
Page 12
For product information and a complete list of distributors, please go to our web site: Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries. Data subject to change. Copyright ...