FAN6210MY Fairchild Semiconductor, FAN6210MY Datasheet
FAN6210MY
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FAN6210MY Summary of contents
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... Personal Computer (PC) Power Supply Entry-Level Server Power Supply Ordering Information Operating Part Number Temperature Range FAN6210MY -40°C to +105°C For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Description FAN6210 is a primary-side SR trigger Integrated Circuit (IC) specially designed for the synchronous rectifier (SR) in dual forward converters employing FAN6206 ...
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... RDLY 4 2/ DET OVP + - 25.5V VDD 10/8V © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Figure 1. Typical Application Rising/Falling Delay 100ns 300ns Controlled Rising Delay GM Rising Delay 50ns One-shot Vibrator Rising/Falling Delay One-shot Vibrator 50ns 50ns Internal Bias Figure 2. Functional Block Diagram ...
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... DET Sensing freewheel diode voltage. 6 VDD The power supply pin. 7 SOUT Gate driving to high- and low-side gate driver. 8 GND Ground. © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Fairchild Logo F: Z: Plant Code X: Year Code Y: Week Code TT: Package Type T: M=SOP P: Y: Green Package M: Manufacture Flow Code Figure 3 ...
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... The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol T Operating Ambient Temperature A © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Parameter < 50°C A Parameter 4 Min ...
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... Delay Time to Trigger XP by SOUT Rising Edge DLY_XP V Output Voltage Maximum (Clamp Output Voltage LOW OL V Output Voltage HIGH OH t SOUT Rising Time R t SOUT Falling Time F © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Parameter OVP DD Stop XP Pulse PLS_OFF 100pF; L SOUT 100pF; ...
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... Temperature℃ Figure 9. High-Level Pulsewidth of XN Signal -40 -25 - Temperature℃ Figure 11. Delay Time to Trigger XN by SIN Rising or Falling Edge © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 = 25°C. A 9.00 8.75 8.50 8.25 8. 110 125 Figure 6. Turn-Off Threshold Voltage 150 140 130 ...
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... Q 2 Figure 13. Simplified Circuit Diagram of Dual-Forward Converter Figure 14. Key Waveforms of Dual-Forward Converter © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Figure 15 shows the typical application circuit of FAN6210. SIN is the gate drive output of the PWM and its key controller. SOUT is obtained from SIN by adding a ...
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... SOUT Programmable delay XP 700ns 50ns XN 300ns Gate drive for Powering SR DET Figure 17. Programmable Delay with Resistor © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Heavy load condition 100ns 50ns 700ns 50ns 300ns Gate drive for Free-wheeling SR Light load condition 100ns ...
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... XP GND 2 XN SOUT OPWM 3 SIN VDD (From FAN480X) 4 RDLY DET 8.2k 1N4148 1N4148 1N4148 1N4148 1N4148 © 2009 Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 Input Voltage Range 90~264V AC FCP20N60 UF1007 10k 74:7 FR107 FCP20N60 68k UF1007 10k 10k 470 1 LPC1GATE1 2 LPC2 GND 0 ...
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... Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’ ...
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... Fairchild Semiconductor Corporation FAN6210 Rev. 1.0.2 11 www.fairchildsemi.com ...