PIC18C601-I/L Microchip Technology, PIC18C601-I/L Datasheet - Page 74

• Manufacturer Part Number: PIC18C601-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,68PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C601-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164309 - MODULE SKT FOR PM3 44PLCCXLT68L1 - SOCKET TRANSITION ICE 68PLCCAC174007 - MODULE SKT PROMATEII 68PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C601I/L

PIC18C601/801
6.1
Several control registers are used in conjunction with
the TBLRD and TBLWT instructions. These include:
• TABLAT register
• TBLPTR registers
6.1.1
The Table Latch (TABLAT) is an 8-bit register mapped
into the SFR space. The Table Latch is used to hold
8-bit data during data transfers between program mem-
ory and data memory.
TABLE 6-1:
DS39541A-page 74
TBLRD*+
TBLWT*+
TBLRD*-
TBLWT*-
TBLRD+*
TBLWT+*
Example
Control Registers
TBLRD*
TBLWT*
TABLAT - TABLE LATCH REGISTER
TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS
TBLPTR is not modified
TBLPTR is incremented after the read/write
TBLPTR is decremented after the read/write
TBLPTR is incremented before the read/write
Advance Information
Operation on Table Pointer
6.1.2
The Table Pointer (TBLPTR) addresses a byte within
the program memory. The TBLPTR is comprised of
three SFR registers (Table Pointer Upper byte, High
byte
(TBLPTRU:TBLPTRH:TBLPTRL) join to form a 21-bit
wide pointer. The 21-bits allow the device to address up
to 2 Mbytes of program memory space.
The table pointer TBLPTR is used by the TBLRD and
TBLWRT instructions. These instructions can update
the TBLPTR in one of four ways, based on the table
operation. These operations are shown in Table 6-1.
These operations on the TBLPTR only affect the low
order 21-bits.
and
TBLPTR - TABLE POINTER
REGISTER
Low
byte).
2001 Microchip Technology Inc.
These
three
registers