PIC18C601-I/L Microchip Technology, PIC18C601-I/L Datasheet - Page 308

• Manufacturer Part Number: PIC18C601-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,68PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C601-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164309 - MODULE SKT FOR PM3 44PLCCXLT68L1 - SOCKET TRANSITION ICE 68PLCCAC174007 - MODULE SKT PROMATEII 68PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C601I/L

PIC18C601/801
C
CALL ................................................................................ 230
Capture (CCP Module) .................................................... 142
Capture/Compare/PWM (CCP) ....................................... 141
Chip Select
Chip Select I/O (CSIO) ...................................................... 71
Chip Selects
Clocking Scheme ............................................................... 46
CLRF ............................................................................... 231
CLRWDT ......................................................................... 231
Code Examples ............................................................... 154
COMF .............................................................................. 232
Compare (CCP Module) .................................................. 144
Configuration Address Map, Example ............................... 71
Configuration Bits ............................................................ 207
Context Saving During Interrupts ..................................... 101
CPFSEQ .......................................................................... 232
CPFSGT .......................................................................... 233
CPFSLT ........................................................................... 233
DS39541A-page 308
Block Diagram ......................................................... 143
CCP Pin Configuration ............................................. 142
CCPR1H:CCPR1L Registers ................................... 142
Changing Between Capture Prescalers ................... 143
Software Interrupt .................................................... 143
Timer1 Mode Selection ............................................ 142
Capture Mode. See Capture
CCP1 ....................................................................... 142
CCP2 ....................................................................... 142
Compare Mode. See Compare
Interaction of Two CCP Modules ............................. 142
PWM Mode. See PWM
Registers Associated with Capture
Timer Resources ..................................................... 142
Timing Diagram ....................................................... 282
Chip Select 2 (CS2) ................................................... 71
Chip Select 1 (CS1) ................................................... 71
Changing Between Capture Prescalers ................... 143
Clearing RAM Using Indirect Addressing .................. 59
Combination Unlock (Macro) ..................................... 51
Combination Unlock (Subroutine) .............................. 50
Fast Register Stack ................................................... 45
Initializing PORTA .................................................... 103
Initializing PORTB .................................................... 105
Initializing PORTC ................................................... 108
Initializing PORTD ................................................... 110
Initializing PORTE .................................................... 113
Initializing PORTF .................................................... 116
Initializing PORTG ................................................... 119
Initializing PORTH ................................................... 121
Initializing PORTJ .................................................... 124
Programming Chip Select Signals ........................... 116
Saving STATUS, WREG and BSR Registers .......... 101
Table Read ................................................................ 75
Table Write ................................................................ 77
Block Diagram ......................................................... 144
CCP Pin Configuration ............................................. 144
CCPR1H:CCPR1L Registers ................................... 144
Software Interrupt .................................................... 144
Special Event Trigger .................... 133
Timer1 Mode Selection ............................................ 144
Table ........................................................................ 207
CCPR1H Register ........................................... 142
CCPR1L Register ............................................ 142
CCPR2H Register ........................................... 142
CCPR2L Register ............................................ 142
and Compare ........................................... 145
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139
Advance Information
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144
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200
D
Data Memory ..................................................................... 49
Data Memory Map
DAW ................................................................................ 234
DC and AC Characteristics Graphs and Tables .............. 295
DCFSNZ .......................................................................... 235
DECF ............................................................................... 234
DECFSZ .......................................................................... 235
Development Support ...................................................... 259
Development Tool Version Requirements ....................... 305
Device Differences .......................................................... 303
Device Migrations ............................................................ 304
Direct Addressing .............................................................. 60
E
Electrical Characteristics ................................................. 265
Errata ................................................................................... 7
External Wait Cycles ......................................................... 72
F
Fast Register Stack ........................................................... 45
Firmware Instructions ...................................................... 215
G
General Call Address Sequence ..................................... 162
General Call Address Support ......................................... 162
GOTO .............................................................................. 236
I
I/O Mode .......................................................................... 119
I/O Ports .......................................................................... 103
I
I
I
I
2
2
2
2
C (SSP Module) ............................................................ 159
C Master Mode Reception ............................................ 167
C Master Mode RESTART Condition ........................... 166
C Module
General Purpose Registers ....................................... 49
Special Function Registers ........................................ 49
Program Bit Not Set .................................................. 51
Program Bit Set ......................................................... 52
ACK Pulse .......................................................159
Addressing .............................................................. 160
Block Diagram ......................................................... 159
Read/Write Bit Information (R/W Bit) ....................... 160
Reception ................................................................ 160
Serial Clock (RC3/SCK/SCL) .................................. 160
Slave Mode ............................................................. 159
Timing Diagram, Data ............................................. 287
Timing Diagram, START/STOP Bits ....................... 287
Transmission ........................................................... 160
Acknowledge Sequence Timing .............................. 170
Baud Rate Generator .............................................. 164
BRG Reset due to SDA Collision ............................ 174
BRG Timing ............................................................. 165
Bus Collision
Bus Collision Timing ................................................ 172
Block Diagram ................................................. 164
Acknowledge ................................................... 172
RESTART Condition ....................................... 175
RESTART Condition Timing (Case1) .............. 175
RESTART Condition Timing (Case2) .............. 175
START Condition ............................................ 173
START Condition Timing ........................173
STOP Condition .............................................. 176
STOP Condition Timing (Case1) ..................... 176
STOP Condition Timing (Case2) ..................... 176
Transmit Timing .............................................. 172
2001 Microchip Technology Inc.
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