PIC18C601-I/L Microchip Technology, PIC18C601-I/L Datasheet - Page 221

• Manufacturer Part Number: PIC18C601-I/L
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,LDCC,68PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Cr

Specifications of PIC18C601-I/L

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Type: ROMless
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• Processor Series: PIC18C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: 3-Wire, I2C, SPI, USART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 47
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: DV164005, ICE4000, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164309 - MODULE SKT FOR PM3 44PLCCXLT68L1 - SOCKET TRANSITION ICE 68PLCCAC174007 - MODULE SKT PROMATEII 68PLCC
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: PIC18C601I/L

20.1
ADDLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2001 Microchip Technology Inc.
Before Instruction
After Instruction
Decode
Instruction Set
WREG
N
OV
C
DC
Z
WREG
N
OV
C
DC
Z
Q1
=
=
=
=
=
=
=
=
=
=
=
=
ADD literal to WREG
[ label ] ADDLW
0
(WREG) + k
N,OV, C, DC, Z
The contents of WREG are added to
the 8-bit literal ’k’ and the result is
placed in WREG.
1
1
literal ’k’
ADDLW
Read
0000
Q2
10h
?
?
?
?
?
25h
0
0
0
0
0
k
255
15h
1111
Process
Data
Q3
WREG
k
kkkk
Advance Information
Write to
WREG
Q4
kkkk
ADDWF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
WREG
REG
N
OV
C
DC
Z
WREG
REG
N
OV
C
DC
Z
Q1
PIC18C601/801
=
=
=
=
=
=
=
=
=
=
=
=
=
=
register ’f’
ADD WREG to f
[ label ] ADDWF
0
d
a
(WREG) + (f)
N,OV, C, DC, Z
Add WREG to register ’f’. If ’d’ is 0,
the result is stored in WREG. If ’d’ is
1, the result is stored back in register
'f' (default). If ’a’ is 0, the Access
Bank will be selected. If ’a’ is 1, the
Bank will be selected as per the BSR
value.
1
1
ADDWF
Read
0010
Q2
17h
0C2h
?
?
?
?
?
0D9h
0C2h
1
0
0
0
0
f
[0,1]
[0,1]
255
01da
REG, W
Process
Data
Q3
DS39541A-page 221
dest
f [,d [,a]]
ffff
destination
Write to
Q4
ffff