DSPIC30F6010-20E/PF Microchip Technology, DSPIC30F6010-20E/PF Datasheet - Page 53
DSPIC30F6010-20E/PF
Manufacturer Part Number
DSPIC30F6010-20E/PF
Description
IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6010A-30IPF.pdf
(22 pages)
2.DSPIC30F6010-20IPF.pdf
(222 pages)
3.DSPIC30F6010-20IPF.pdf
(30 pages)
4.DSPIC30F4011-20IML.pdf
(236 pages)
Specifications of DSPIC30F6010-20E/PF
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F601020EPF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F6010A-30IPF PDF datasheet
- DSPIC30F6010-20IPF PDF datasheet #2
- DSPIC30F6010-20IPF PDF datasheet #3
- DSPIC30F4011-20IML PDF datasheet #4
- Current page: 53 of 236
- Download datasheet (4Mb)
7.0
The data EEPROM memory is readable and writable
during normal operation over the entire V
data EEPROM memory is directly mapped in the
program memory address space.
The four SFRs used to read and write the program
Flash memory are used to access data EEPROM
memory, as well. As described in Section 6.0 “Flash
Program Memory”, these registers are:
• NVMCON
• NVMADR
• NVMADRU
• NVMKEY
The EEPROM data memory allows read and write of
single words and 16-word blocks. When interfacing to
data memory, NVMADR, in conjunction with the
NVMADRU register, is used to address the EEPROM
location being accessed. TBLRDL and TBLWTL instruc-
tions are used to read and write data EEPROM. The
dsPIC30F4011/4012 devices have 1 Kbyte (512 words)
of data EEPROM, with an address range from
0x7FFC00 to 0x7FFFFE.
A word write operation should be preceded by an erase
of the corresponding memory location(s). The write
typically requires 2 ms to complete, but the write time
will vary with voltage and temperature.
A program or erase operation on the data EEPROM
does not stop the instruction flow. The user is respon-
sible for waiting for the appropriate duration of time
before initiating another data EEPROM write/erase
operation. Attempting to read the data EEPROM while
a programming or erase operation is in progress results
in unspecified data.
© 2007 Microchip Technology Inc.
Note: This data sheet summarizes features of this group
of dsPIC30F devices and is not intended to be a complete
reference source. For more information on the CPU,
peripherals, register descriptions and general device
functionality, refer to the dsPIC30F Family Reference
Manual (DS70046). For more information on the device
instruction set and programming, refer to the “dsPIC30F/
33F Programmer’s Reference Manual” (DS70157).
DATA EEPROM MEMORY
DD
range. The
Control bit, WR, initiates write operations, similar to
program Flash writes. This bit cannot be cleared, only
set, in software. This bit is cleared in hardware at the
completion of the write operation. The inability to clear
the WR bit in software prevents the accidental or
premature termination of a write operation.
The WREN bit, when set, will allow a write operation.
On power-up, the WREN bit is clear. The WRERR bit is
set when a write operation is interrupted by a MCLR
Reset, or a WDT Time-out Reset, during normal oper-
ation. In these situations, following Reset, the user can
check the WRERR bit and rewrite the location. The
address register, NVMADR, remains unchanged.
7.1
A TBLRD instruction reads a word at the current pro-
gram word address. This example uses W0 as a
pointer to data EEPROM. The result is placed in
register W4, as shown in Example 7-1.
EXAMPLE 7-1:
MOV
MOV
MOV
TBLRDL [ W0 ], W4
Note:
dsPIC30F4011/4012
Reading the Data EEPROM
#LOW_ADDR_WORD,W0
#HIGH_ADDR_WORD,W1
W1
,
Interrupt flag bit, NVMIF in the IFS0 regis-
ter, is set when write is complete. It must
be cleared in software.
TBLPAG
DATA EEPROM READ
; Init Pointer
; read data EEPROM
DS70135E-page 51
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