DSPIC30F6010-20E/PF Microchip Technology, DSPIC30F6010-20E/PF Datasheet - Page 16
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DSPIC30F6010-20E/PF
Manufacturer Part Number
DSPIC30F6010-20E/PF
Description
IC,DSP,16-BIT,CMOS,TQFP,80PIN,PLASTIC
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.DSPIC30F6010A-30IPF.pdf
(22 pages)
2.DSPIC30F6010-20IPF.pdf
(222 pages)
3.DSPIC30F6010-20IPF.pdf
(30 pages)
4.DSPIC30F4011-20IML.pdf
(236 pages)
Specifications of DSPIC30F6010-20E/PF
Rohs Compliant
YES
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
68
Program Memory Size
144KB (48K x 24)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
80-TQFP, 80-VQFP
Package
80TQFP
Device Core
dsPIC
Family Name
dsPIC30
Maximum Speed
20 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16 Bit
Interface Type
CAN/I2C/SPI/UART
On-chip Adc
16-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300019 - BOARD DEMO DSPICDEM 80L STARTERAC164314 - MODULE SKT FOR PM3 80PFDM300020 - BOARD DEV DSPICDEM MC1 MOTORCTRLAC30F001 - MODULE SOCKET DSPIC30F 80TQFPXLT80PT2 - SOCKET TRANSITION ICE 80TQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC30F601020EPF
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
DSPIC30F6010-20E/PF
Manufacturer:
Microchip Technology
Quantity:
10 000
- DSPIC30F6010A-30IPF PDF datasheet
- DSPIC30F6010-20IPF PDF datasheet #2
- DSPIC30F6010-20IPF PDF datasheet #3
- DSPIC30F4011-20IML PDF datasheet #4
- Current page: 16 of 236
- Download datasheet (4Mb)
dsPIC30F4011/4012
2.2
The programmer’s model is shown in Figure 2-1 and
consists of 16x16-bit working registers (W0 through
W15), 2x40-bit accumulators (ACCA and ACCB),
STATUS register (SR), Data Table Page register
(TBLPAG), Program Space Visibility Page register
(PSVPAG), DO and REPEAT registers (DOSTART,
DOEND, DCOUNT and RCOUNT) and Program
Counter (PC). The working registers can act as data,
address or offset registers. All registers are memory
mapped. W0 acts as the W register for file register
addressing.
Some of these registers have a shadow register asso-
ciated with each of them, as shown in Figure 2-1. The
shadow register is used as a temporary holding register
and can transfer its contents to or from its host register
upon the occurrence of an event. None of the shadow
registers are accessible directly. The following rules
apply for transfer of registers into and out of shadows.
• PUSH.S and POP.S
• DO instruction
When a byte operation is performed on a working
register, only the Least Significant Byte of the target
register is affected. However, a benefit of memory
mapped working registers is that both the Least and
Most Significant Bytes can be manipulated through
byte wide data memory space accesses.
DS70135E-page 14
W0, W1, W2, W3, SR (DC, N, OV, Z and C bits
only) are transferred.
DOSTART, DOEND, DCOUNT shadows are
pushed on loop start and popped on loop end.
Programmer’s Model
2.2.1
The dsPIC
ware stack. W15 is the dedicated software Stack
Pointer (SP) and is automatically modified by exception
processing and subroutine calls and returns. However,
W15 can be referenced by any instruction in the same
manner as all other W registers. This simplifies the
reading, writing and manipulation of the Stack Pointer
(e.g., creating stack frames).
W15 is initialized to 0x0800 during a Reset. The user
may reprogram the SP during initialization to any
location within data space.
W14 has been dedicated as a Stack Frame Pointer as
defined by the LNK and ULNK instructions. However,
W14 can be referenced by any instruction in the same
manner as all other W registers.
2.2.2
The dsPIC DSC core has a 16-bit STATUS register (SR),
the Least Significant Byte of which is referred to as the
SR Low Byte (SRL) and the Most Significant Byte as the
SR High Byte (SRH). See Figure 2-1 for SR layout.
SRL contains all the DSP ALU operation Status flags
(including the Z bit), as well as the CPU Interrupt Prior-
ity Level Status bits, IPL<2:0>, and the Repeat Active
Status bit, RA. During exception processing, SRL is
concatenated with the MSB of the PC to form a
complete word value which is then stacked.
The upper byte of the SR register contains the DSP
Adder/Subtracter Status bits, the DO Loop Active bit
(DA) and the Digit Carry (DC) Status bit.
2.2.3
The Program Counter is 23 bits wide. Bit 0 is always
clear; therefore, the PC can address up to 4M
instruction words.
Note:
®
SOFTWARE STACK POINTER/
FRAME POINTER
In order to protect against misaligned
stack accesses, W15<0> is always clear.
STATUS REGISTER
PROGRAM COUNTER
Digital Signal Controllers contain a soft-
© 2007 Microchip Technology Inc.
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