CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 49

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SDATA (fig. 2)
addition, an appropriate baud clock needs to be
input to the CS5501. See AC (Asynchronous
Communication) mode mentioned earlier for an
explanation of the baud rate clock generator and
the data format of the output data in the AC
mode.
The DRDY output from the CS5501 signals the
CTS (Clear To Send) line of the RS-232 interface
when data is available. The Decimation Counter
can be used to determine how frequently output
data is to be transmitted.
The RS-232 interface on the evaluation card is
functionally adequate but it is not compliant with
the EIA RS-232 standard. When the MC145406
RS-232 receiver/driver chip is operated off of
volt supplies rather than
MC145406 data sheet for details) its driver output
swing is reduced below the EIA specified limits.
In practical applications this signal swing limita-
tion only reduces the length of cable the circuit is
capable of driving.
DS31DB3
DRDY (fig. 2)
V+
V-
RN 1.5
Figure 4. RS-232 Port
V+
15
0.1 F
0.1 F
47 k
9
10
16
12
U11C
U11F
14
U11B
MC145406
11
1
8
U11A
13
2
U11E
7
6 volts (see the
U11D
5
3
6
4
NC
DATA
DCD
DSR
CTS
DTR
RTS
Sub-D
25 pin
3
5
6
8
4
7
1
P6
20
5
DECIMATION COUNTER
Each time a data word is available for output
from the CS5501/CS5503, the DRDY line goes
low, provided the output port was previously
emptied. If the DRDY line is directly tied to the
CS input of the CS5501/CS5503, the converter
will output data every time a data word is pre-
sented to the output pin. In some applications it is
desirable to reduce the output word rate. The rate
Decimation Counter Accumulates 2
Enabled.
can be reduced by lowering the rate at which the
CS line to the chip is enabled. The
CDB5501/CDB5503 evaluation board uses a
counter, IC U3 for this purpose. It is known as a
decimation counter (see Figure 2). The outputs of
the counter are available at connector P4. The
counter accumulates 2n+1 counts (n = 0, 2,
at which time the selected output enables the CS
input to the CS5501/CS5503 (if the jumper in P9
is in the DC, Decimation Counter, position). The
P-4
P-9
NC
DC
10
11
0
1
2
3
4
5
6
7
8
9
Table 4. Decimation Counter Control
DC Output to CS
No Connection
Decimation Counter
CDB5501/CDB5503
n+1
DRDY Pulses Before CS is
1024
2048
4096
2
128
256
512
16
32
64
n+1
2
4
8
11)
49