CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 14

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Note: 1. There are 16 analog and digital settling periods per filter cycle (4 are shown). Data can be output in the
The eighth output window time overlaps the time
in which the serial output port is to be updated. If
the CS is recognized as being low when it is
polled for the eighth window time, data will be
output as normal, but the serial port will not be
updated with new data until the next serial port
update time. Under these conditions, the serial
port will experience an update rate of only 2 kHz
14
SDATA (o)
SDATA (o)
DRDY (o)
SCLK (o)
SCLK (o)
CS5501
CS5501
CS5503
CS5503
Internal
Status
CLKIN (i)
DRDY (o)
CS (i)
SDATA (o)
SCLK (o)
CS (i)
SSC mode in only 1 of the 8 digital time periods in each filter cycle.
**
Hi-Z
Hi-Z
Hi-Z
Hi-Z
*
CS5501
CS5503
76 CLKIN cycles
Analog Time 0
76/CLKIN
64/CLKIN
Hi-Z
Hi-Z
Figure 5. Synchronous Self-Clocking (SSC) Mode Timing
Note 1
B15*
B19**
(MSB)
(MSB)
(MSB)
Digital Time 0
Figure 4. Internal Timing
64/CLKIN
CS Polled
B14*
B18**
(LSB)
f
out
=1024/CLKIN
(CLKIN = 4.096 MHz) instead of the normal
4 kHz serial port update rate.
Upon completion of transmission of all the data
bits, the SCLK and SDATA outputs will go to a
high impedance state even with CS held low. In
the event that CS is taken high before all data bits
are output, the SDATA and SCLK outputs will
(LSB)
Analog Time 1
Hi-Z
Hi-Z
Hi-Z
Hi-Z
B1
Digital Time1
(LSB)
CS5501/CS5503
B0
Hi-Z
Hi-Z
DS31F2