CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 30

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

SDATA -Serial Data Output, Pin 20.
SCLK -Serial Clock Input/Output, Pin 19.
Calibration Control Inputs
SC1; SC2 -System Calibration 1 and 2, Pins 4 and 17.
BP/UP -Bipolar/Unipolar Select, Pin 12.
CAL -Calibrate, Pin 13.
Other Control Input
SLEEP -Sleep, Pin 11.
Analog Inputs
VREF -Voltage Reference, Pin 10.
AIN -Analog Input, Pin 9.
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Data from the serial port will be output from this pin at a rate determined by SCLK and in a
format determined by the MODE pin. It furnishes a high impedance output state when not
transmitting data.
A clock signal at this pin determines the output rate of the data from the SDATA pin. The
MODE pin determines whether the SCLK signal is an input or output. SCLK may provide a
high impedance output when data is not being output from the SDATA pin.
Control inputs to the CS5501/CS5503’s calibration microcontroller for calibration. The state of
SC1 and SC2 determine which of the calibration modes is selected for operation (see Table 2).
Determines whether the CS5501/CS5503 will be calibrated to measure bipolar (BP/UP = VD+)
or unipolar (BP/UP = DGND) input signals. Recalibration is necessary whenever the state of
BP/UP is changed.
If brought high for 4 clock cycles or more, the CS5501/CS5503 will reset and upon returning
low a full calibration cycle will begin. The state of SC1, SC2, and BP/UP when CAL is
brought low determines the type and length of calibration cycle initiated (see Table 2). Also, a
single CAL signal can be used to strobe the CAL pins high on several CS5501/CS5503’s to
synchronize their operation. Any spurious glitch on this pin may inadvertently place the chip in
Calibration mode.
When brought low, the CS5501/CS5503 will enter a low-power state. When brought high
again, the CS5501/CS5503 will resume operation without the need to recalibrate. After SLEEP
goes high again, the device’s output will settle to within +0.0007% of the analog input value
within 1.3/f
synchronize sampling and the output updates of several CS5501/CS5503’s.
Analog reference voltage input.
-3dB
, where f
-3dB
is the passband frequency. The SLEEP input can also be used to
CS5501/CS5503
DS31F2