CS5501-BS Cirrus Logic Inc, CS5501-BS Datasheet - Page 21

• Manufacturer Part Number: CS5501-BS
• Description: A/D Converter (A-D) IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS5501-BS

• Peak Reflow Compatible (260 C): No
• No. Of Bits: 16 Bit
• Leaded Process Compatible: No
• Mounting Type: Surface Mount
• Interface Type: Serial
• Package / Case: 20-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

+ or -) a clamp diode will be forward-biased. Un-
der these fault conditions the CS5501/CS5503
might be damaged. Under normal operating con-
ditions (with the power supplies established), the
device will survive transient currents through the
clamp diodes up to 100 mA and continuous cur-
rents up to 10 mA. The drive current into the AIN
pin should be limited to a safe value if an over-
voltage condition is likely to occur. See the
application note "Buffer Amplifiers for the
CS501X Series of A/D Converters" for further
discussion on the clamp diode input structure and
on current limiting circuits.
System Synchronization
If more than one CS5501/CS5503 is included in a
system which is operating from a common clock,
all of the devices can be synchronized to sample
and output at exactly the same time. This can be
accomplished in either of two ways. First, a single
CAL signal can be issued to all the
CS5501/CS5503’s in the system. To insure syn-
chronization on the same clock signal the CAL
signal should go low on the falling edge of
CLKIN. Or second, a common SLEEP control
signal can be issued. If the SLEEP signal goes
positive with the appropriate set up time to
CLKIN, all parts will be synchronized on the
same clock cycle.
Analog Input Impedance Considerations
The analog input of the CS5501/CS5503 can be
modeled as illustrated in Figure 11. A 20 pF ca-
pacitor is used to dynamically sample the input
signal. Every 64 CLKIN cycles the switch alter-
nately connects the capacitor to the output of the
buffer and then directly to the AIN pin. When-
ever the sample capacitor is switched from the
output of the buffer to the AIN pin, a small packet
of charge (a dynamic demand of current) will be
required from the input source to settle the volt-
age on the sample capacitor to its final value.
The voltage at the output of the buffer may differ
up to 100 mV from the actual input voltage due to
DS31F2
the offset voltage of the buffer. Timing allows 64
cycles of master clock (CLKIN) for the voltage
on the sample capacitor to settle to its final value.
The equation which defines settling time is:
Where Ve is the final settled value, V
maximum error voltage value of the input signal,
R is the value of the input source resistance, C is
the 20 pF sample capacitor plus the value of any
stray or additional capacitance at the input pin.
The value of t is equal to 64/CLKIN.
V
tor is switched from the buffer output to the AIN
pin. Prior to the switch, AIN has an error esti-
mated as being less than or equal to V
equal to the prior error (V
error from the buffer offset. The estimate for
V
Where C
or stray capacitance.
From the equation which defines settling time, an
equation for the maximum acceptable source re-
sistance is derived
max
max
is:
occurs the instance when the sample capaci-
AGND
AIN
EXT
V
Figure 11. Analog Input Model
max
is the combination of any external
V
V
e
e
V
100mV
+
-
os
V
max
100 mv
CS5501/CS5503
CS5503
CS5501
e
e
20pF C
) plus the additional
t RC
20 pF
20pF
EXT
e
max
. V
max
is the
21
is