NRF9E5 NORDIC SEMICONDUCTOR, NRF9E5 Datasheet - Page 75

• Manufacturer Part Number: NRF9E5
• Description: TRX, 430-928MHZ, MCU/ADC/PWM, SMD
• Manufacturer: NORDIC SEMICONDUCTOR

Specifications of NRF9E5

• Receiving Current: 12.5mA
• Transmitting Current: 30mA
• Data Rate: 50Kbps
• Frequency Range: 430MHz To 928MHz
• Modulation Type: GFSK
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Supply Voltage Range: 1.9V To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
18.7 SFR Registers Unique to nRF9E5
The table below lists the SFR registers that are unique to nRF9E5 (not part of standard
8051 register map) The registers P0, P1 and P2 (radio) use the addresses for the ports
P0, P1 and P2 in a standard 8051. Whereas the functionality of these ports is similar to
that of the corresponding ports in standard 8051, it is not identical.
*
**
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone [phone] - Fax [phone]
Revision: 1.3
Addr
SFR
A0*
90*
AA
AD
80
AB
AC
A9
BF
B1
B2
B3
B4
B5
B6
B7
FE
94
95
96
97
*
This bit addressable register differs in usage from “standard 8051”
Only 4 lower bits are meaningful in P1 and corresponding P1_DIR and P1_ALT
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
#bit
8(4)
8(4)
8(4)
8
8
8
8
8
8
8
8
5
2
8
2
2
8
3
4
6
8
Table 64 SFR registers unique to nRF9E5.
Init
hex
1D
FF
FF
FF
F4
00
00
08
02
27
00
0
0
0
0
0
0
0
0
0
0
REGX_CTRL
TEST_MODE
REGX_MSB
PWMDUTY
REGX_LSB
SPI_DATA
CKLFCON
PWMCON
SPI_CTRL
CK_CTRL
RSTREAS
TICK_DV
HWREV
P0_ALT
P1_ALT
SPICLK
P0_DIR
P1_DIR
Name
P1**
P0
P2
Page 75 of 108
This register must always be 0 in normal mode.
Select alternate functions for each pin of port 0
Select alternate functions for each pin of port 1
Port 1, pins SPI_CSN, SPI_MISO, SPI_MOSI
General purpose I/O for interface to nRF905
Control of interface to Watchdog and RTC.
High part of 16 bit register for interface to
Low part of 16 bit register for interface to
00 -> SPI not used
Divider from CPU clock to SPI clock
Direction for each GPIO bit of port 1
Direction of each GPIO bit of port 0
Control generation of 4 kHz CKLF
radio, for details see chapter 8.1
10 or 11 -> connect to RADIO
Reset status and control
Port 0, pins P07 to P00
PWM control register
SPI data input/output
Watchdog and RTC
Watchdog and RTC
Test mode register.
PWM duty cycle
Silicon stepping
TICK Divider.
and SPI_SCK
Clock control
Function
01 -> connect to P1
June 2006