AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 20

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.2.3.2
1.2.3.3
1.2.4
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them. Processor accesses to the default IOAPIC region (FEC0_0000h to FECF_FFFFh)
are always forwarded to DMI.
HSEG (FEDA_0000h-FEDB_FFFFh)
This optional segment from FEDA_0000h to FEDB_FFFFh provides a remapping
window to SMM Memory. It is sometimes called the High SMM memory space. SMM-
mode CPU accesses to the optionally enabled HSEG are remapped to 000A¬_0000h -
000B_FFFFh. Non-SMM-mode CPU accesses to enabled HSEG are considered invalid
and are terminated immediately. The exceptions to this rule are Non-SMM-mode Write
Back cycles, which are remapped to SMM space to maintain cache coherency. DMI
originated cycles to enable SMM space are not allowed. Physical DRAM behind the
HSEG transaction address is not remapped and is not accessible. All cache line writes
with WB attribute or Implicit write backs to the HSEG range are completed to DRAM
like an SMM cycle.
High BIOS Area
The top 2 MB (FFE0_0000h -FFFF_FFFFh) of the PCI Memory Address Range is
reserved for System BIOS (High BIOS), extended BIOS for PCI devices, and the A20
alias of the system BIOS. The CPU begins execution from the High BIOS after reset.
This region is mapped to DMI Interface so that the upper subset of this region aliases
to 16 MB-256 KB range. The actual address space required for the BIOS is less than 2
MB but the minimum CPU MTRR range for this region is 2 MB so that full 2 MB must
be considered.
Main Memory Address Space (4 GB to TOUUD)
The processor supports 36-bit addressing.
The maximum main memory size supported is 8 GB total DRAM memory. A hole
between TOLUD and 4 GB occurs when main memory size approaches 4 GB or larger.
As a result, TOM, and TOUUD registers and RECLAIMBASE/RECLAIMLIMIT registers
become relevant.
The new reclaim configuration registers exist to reclaim lost main memory space. The
greater than 32 bit reclaim handling will be handled similar to previous MCHs.
Upstream read and write accesses above 36-bit addressing will be treated as invalid
cycles by DMI.
Top of Memory
The “Top of Memory” (TOM) register reflects the total amount of populated physical
memory. This is NOT necessarily the highest main memory address (holes may exist
in main memory address map due to addresses allocated for memory mapped IO
above TOM).
The Top of Upper Usable Dram (TOUUD) register reflects the total amount of
addressable DRAM. If reclaim is disabled, TOUUD will reflect TOM. If reclaim is
enabled, then it will reflect the reclaim limit. In addition, the reclaim base will be the
same as TOM.
Processor Configuration Registers
Datasheet