AU80610004392AAS LBLA Intel, AU80610004392AAS LBLA Datasheet - Page 15

• Manufacturer Part Number: AU80610004392AAS LBLA
• Description: MPU, ATOM PRO, DUALCORE, D510, FC-BGA8
• Manufacturer: Intel
• Series: ATOM - D500r

Specifications of AU80610004392AAS LBLA

• Core Size: 64bit
• Cpu Speed: 1.66GHz
• Digital Ic Case Style: BGA
• No. Of Pins: 559
• Operating Temperature Range: 0°C To +100°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Processor Configuration Registers
1.2.1.5
1.2.1.6
1.2.2
Datasheet
Table 1-2. Extended System BIOS Area Memory Segments
Table 1-3. System BIOS Area Memory Segments
Non-snooped accesses from DMI to this region are always sent to DRAM.
System BIOS Area (F_0000h-F_FFFFh)
This area is a single 64 KByte segment (000F_0000h – 000F_FFFFh). This segment
can be assigned read and write attributes. It is by default (after reset) Read/Write
disabled and cycles are forwarded to DMI Interface. By manipulating the Read/Write
attributes, the IMC can “shadow” BIOS into the main DRAM. When disabled, this
segment is not remapped.
Non-snooped accesses from DMI to this region are always sent to DRAM.
PAM Memory Area Details
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM
Memory Area.
The IMC does not handle Implicit Write-Back (IWB) cycles targeting DMI. Since all
memory residing on DMI should be set as non-cacheable, there will normally not be
IWB cycles targeting DMI.
However, DMI becomes the default target for CPU and DMI originated accesses to
disabled segments of the PAM region. If the MTRRs covering the PAM regions are set
to WB or RD it is possible to get IWB cycles targeting DMI. This may occur for CPU
originated cycles (in a DP system) and for DMI originated cycles to disabled PAM
regions.
For example, say that a particular PAM region is set for “Read Disabled” and the MTRR
associated with this region is set to WB. A DMI master generates a memory read
targeting the PAM region. Since the PAM region is “Read Disabled” the default target
for the Memory Read becomes DMI. The IWB associated with this cycle will cause the
IMC to hang.
Main Memory Address Range (1 MB - TOLUD)
This address range extends from 1 MB to the top of Low Usable physical memory that
is permitted to be accessible by the IMC (as programmed in the TOLUD register). All
0E0000H – 0E3FFFH
0E4000H – 0E7FFFH
0E8000H – 0EBFFFH
0EC000H – 0EFFFFH
0F0000H – 0FFFFFH
Memory Segments
Memory Segments
WE RE
WE RE
WE RE
WE RE
WE RE
Attributes
Attributes
BIOS Extension
BIOS Extension
BIOS Extension
BIOS Extension
BIOS Area
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