UPD78F0886GA(A)-GAM-AX NEC, UPD78F0886GA(A)-GAM-AX Datasheet - Page 114

8BIT MCU, 60K FLASH, 3KB RAM, CAN

UPD78F0886GA(A)-GAM-AX

Manufacturer Part Number
UPD78F0886GA(A)-GAM-AX
Description
8BIT MCU, 60K FLASH, 3KB RAM, CAN
Manufacturer
NEC
Datasheet

Specifications of UPD78F0886GA(A)-GAM-AX

Controller Family/series
UPD78F
No. Of I/o's
41
Ram Memory Size
3KB
Cpu Speed
20MHz
No. Of Timers
8
No. Of Pwm Channels
6
Digital Ic Case Style
LQFP
Core Size
8bit
Program Memory Size
60KB
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
114
[Instruction format]
[Operation]
[Operand]
[Flag]
[Description]
[Description example]
BTCLR
• If the 1st operand (bit) contents have been set (1), they are cleared (0) and branched to the address specified
• When the 1st operand (bit) is PSW.bit, the corresponding flag contents are cleared (0).
BTCLR PSW.0, $356H; When bit 0 (CY flag) of PSW is 1, the CY flag is cleared to 0 and branched to address
bit =PSW.bit
by the 2nd operand.
If the 1st operand (bit) contents have not been set (1), no processing is carried out and the subsequent
instruction is executed.
Mnemonic
Z
BTCLR
×
AC
×
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
[HL].bit, $addr16
Operand(bit,$addr16)
BTCLR bit, $addr16
PC ← PC+b+jdisp8 if bit = 1, then bit ← 0
CY
×
0356H (with the start of this instruction set in the range of addresses 02D4H to
03D3H).
CHAPTER 5 EXPLANATION OF INSTRUCTIONS
In all other cases
Conditional Branch and Clear by Bit Test (Byte Data Bit = 1)
User's Manual U12326EJ4V0UM
Z
b(Number of bytes)
AC
4
4
3
4
3
CY
Branch if True and Clear

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