PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 426
PIC18F85K22-I/PT
Manufacturer Part Number
PIC18F85K22-I/PT
Description
IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Datasheet
1.PIC18F85K22-IPT.pdf
(550 pages)
Specifications of PIC18F85K22-I/PT
Controller Family/series
PIC18
No. Of I/o's
69
Eeprom Memory Size
1KB
Ram Memory Size
2KB
Cpu Speed
64MHz
No. Of Timers
8
Core Size
8 Bit
Program Memory Size
32KB
Core Processor
PIC
Speed
64MHz
Connectivity
EBI/EMI, I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
69
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 24x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F85K22-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F85K22-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
Company:
Part Number:
PIC18F85K22-I/PTRSL
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F87K22 FAMILY
28.6
The user program memory is divided into four blocks
for the PIC18FX5K22 and PIC18FX6K22 devices, and
eight blocks for PIC18FX7K22 devices. One of these is
a boot block of 1 or 2 Kbytes. The remainder of the
memory is divided into blocks on binary boundaries.
FIGURE 28-6:
DS39960D-page 426
Note 1: Sizes of memory areas are not to scale.
000000h
01FFFFh
200000h
3FFFFFh
Program Verification and
Code Protection
2: Boot block size is determined by the BBSIZ0 bit (CONFIG4L<4>).
Unimplemented
Code Memory
Configuration
Read as ‘ 0 ’
and ID
Space
CODE-PROTECTED PROGRAM MEMORY FOR THE PIC18F87K22 FAMILY
BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0 BBSIZ = 1 BBSIZ = 0
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block
2 kW
6 kW
8 kW
8 kW
8 kW
8 kW
8 kW
8 kW
8 kW
Boot
PIC18FX7K22
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 7
Block
7 kW
8 kW
8 kW
8 kW
8 kW
8 kW
8 kW
8 kW
Boot
locations of the bits are summarized in
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPx)
• Write-Protect bit (WRTx)
• External Block Table Read bit (EBTRx)
Figure 28-6
48, 64, 96 and 128 Kbyte devices and the specific code
protection bit associated with each block. The actual
Device/Memory Size
Block 0
Block 1
Block 2
Block 3
Block
2 kW
6 kW
8 kW
8 kW
8 kW
Boot
PIC18FX6K22
shows the program memory organization for
Block 0
Block 1
Block 2
Block 3
Block
7 kW
8 kW
8 kW
8 kW
Boot
2009-2011 Microchip Technology Inc.
(2)
Block 0
Block 1
Block 2
Block 3
Block
2 kW
2 kW
4 kW
4 kW
4 kW
Boot
PIC18FX5K22
Block 0
Block 1
Block 2
Block 3
Block
3 kW
4 kW
4 kW
4 kW
Boot
Table
0000h
0800h
1000h
17FFh
1800
3FFF
4000h
5FFFh
6000h
7FFF
8000h
BFFFh
C000h
FFFFh
10000h
13FFFh
14000h
17FFFh
18000h
1BFFFh
1C000h
1FFFFh
Address
28-4.
(1)
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