PIC18F85K22-I/PT Microchip Technology, PIC18F85K22-I/PT Datasheet - Page 131

• Manufacturer Part Number: PIC18F85K22-I/PT
• Description: IC, 8BIT MCU, PIC18F, 64MHZ, TQFP-80
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 18Fr

Specifications of PIC18F85K22-I/PT

• Controller Family/series: PIC18
• No. Of I/o's: 69
• Eeprom Memory Size: 1KB
• Ram Memory Size: 2KB
• Cpu Speed: 64MHz
• No. Of Timers: 8
• Core Size: 8 Bit
• Program Memory Size: 32KB
• Core Processor: PIC
• Speed: 64MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 24x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.8
In alternate, power-managed Run modes, the external
bus continues to operate normally. If a clock source
with a lower speed is selected, bus operations will run
at that speed. In these cases, excessive access times
for the external memory may result if Wait states have
been enabled and added to external memory opera-
tions. If operations in a lower power Run mode are
anticipated, users should provide in their applications
for adjusting memory access times at the lower clock
speeds.
TABLE 8-3:
 2009-2011 Microchip Technology Inc.
MEMCON
PADCFG1
PMD1
Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during External Memory Bus access.
Note 1:
Name
Operation in Power-Managed
Modes
(1)
Unimplemented in 64-pin devices (PIC18F6XK22), read as ‘0’.
PSPMD
EBDIS
RDPU
Bit 7
REGISTERS ASSOCIATED WITH THE EXTERNAL MEMORY BUS
CTMUMD
REPU
Bit 6
—
RTCCMD TMR4MD
RJPU
WAIT1
Bit 5
(1)
WAIT0
Bit 4
—
PIC18F87K22 FAMILY
In Sleep and Idle modes, the microcontroller core does
not need to access data; bus operations are
suspended. The state of the external bus is frozen, with
the address/data pins, and most of the control pins,
holding at the same state they were in when the mode
was invoked. The only potential changes are to the CE,
LB and UB pins, which are held at logic high.
TMR3MD
Bit 3
—
—
RTSECSEL1 RTSECSEL0
TMR2MD
Bit 2
—
TMR1MD
WM1
Bit 1
DS39960D-page 131
EMBMD
WM0
Bit 0
—