GS816032BGT-200 GSI TECHNOLOGY, GS816032BGT-200 Datasheet

GS816032BGT-200

Manufacturer Part Number

GS816032BGT-200

Description

18M SYNCH BURST SRAM 512KX32, SMD

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS816032BGT-200.pdf (24 pages)

Specifications of GS816032BGT-200

Memory Size

18Mbit

Clock Frequency

200MHz

Access Time

6.5ns

Supply Voltage Range

2.3V To 2.7V, 3V To 3.6V

Memory Case Style

TQFP

No. Of Pins

100

Operating Temperature Range

0Â°C To +70Â°C

Memory Configuration

512K X 32

Rohs Compliant

Yes

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

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100-Pin TQFP

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline

• Single Cycle Deselect (SCD) operation

• 2.5 V or 3.3 V +10%/–10% core power supply

• 2.5 V or 3.3 V I/O supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 100-lead TQFP package

• RoHS-compliant 100-lead TQFP package available

Functional Description

Applications

The GS816018/32/36BT is an 18,874,368-bit (16,777,216-bit

for x32 version) high performance synchronous SRAM with a

2-bit burst address counter. Although of a type originally

developed for Level 2 Cache applications supporting high

performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main

store to networking chip set support.

Controls

Addresses, data I/Os, chip enables (E1, E2, E3), address burst

control inputs (ADSP, ADSC, ADV), and write control inputs

(Bx, BW, GW) are synchronous and are controlled by a

positive-edge-triggered clock input (CK). Output enable (G)

and power down control (ZZ) are asynchronous inputs. Burst

Rev: 1.03 9/2005

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

operation

Flow Through

Pipeline

3-1-1-1

2-1-1-1

1M x 18, 512K x 32, 512K x 36

18Mb Sync Burst SRAMs

Curr

tCycle

Parameter Synopsis

(x32/x36)

(x18)

1/24

cycles can be initiated with either ADSP or ADSC inputs. In

Burst mode, subsequent burst addresses are generated

internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or

interleave order with the Linear Burst Order (LBO) input. The

Burst function need not be used. New addresses can be loaded

on every cycle with no degradation of chip performance.

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by

the user via the FT mode pin (Pin 14). Holding the FT mode

pin low places the RAM in Flow Through mode, causing

output data to bypass the Data Output Register. Holding FT

high places the RAM in Pipeline mode, activating the rising-

edge-triggered Data Output Register.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable

(BW) input combined with one or more individual byte write

signals (Bx). In addition, Global Write (GW) is available for

writing all bytes at one time, regardless of the Byte Write

control inputs.

Sleep Mode

Low power (Sleep mode) is attained through the assertion

(High) of the ZZ signal, or by stopping the clock (CK).

Memory data is retained during Sleep mode.

Core and Interface Voltages

The GS816018/32/36BT operates on a 2.5 V or 3.3 V power

supply. All input are 3.3 V and 2.5 V compatible. Separate

output power (V

from the internal circuits and are 3.3 V and 2.5 V compatible.

-250

295

345

225

255

2.5

4.0

5.5

-200

245

285

200

220

3.0

5.0

6.5

DDQ

GS816018/32/36BT-250/200/150

) pins are used to decouple output noise

-150

200

225

185

205

3.8

6.7

7.5

Unit

250 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS816032BGT-200

GS816032BGT-200 Summary of contents

Page 1

... Curr (x18) 255 220 Curr (x32/x36) 1/24 GS816018/32/36BT-250/200/150 250 MHz–150 MHz 3.3 V I/O ) pins are used to decouple output noise DDQ -150 Unit 3.8 ns 6.7 ns 200 mA 225 mA 7.5 ns 7.5 ns 185 mA 205 mA © 2004, GSI Technology DD ...

Page 2

... DDQ DDQ DDQ DQP DDQ Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816018B 100-Pin TQFP Pinout Top View 2/24 GS816018/32/36BT-250/200/150 DDQ DQP DDQ DDQ DDQ © 2004, GSI Technology ...

Page 3

... DDQ DDQ DDQ DDQ Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816032B 100-Pin TQFP Pinout 512K x 32 Top View 3/24 GS816018/32/36BT-250/200/150 DDQ DDQ DDQ DDQ © 2004, GSI Technology ...

Page 4

... V 20 DDQ DDQ DQP Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816036B 100-Pin TQFP Pinout 512K x 36 Top View 4/24 GS816018/32/36BT-250/200/150 DQP DDQ DDQ DDQ DDQ DQP 51 A © 2004, GSI Technology ...

Page 5

... Burst address counter advance enable; active low Address Strobe (Processor, Cache Controller); active low Sleep Mode control; active high Flow Through or Pipeline mode; active low Linear Burst Order mode; active low Core power supply I/O and Core Ground Output driver power supply 5/24 © 2004, GSI Technology ...

Page 6

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816018/32/36B Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register 6/24 GS816018/32/36BT-250/200/150 A Memory Array – DQx1 DQx9 © 2004, GSI Technology ...

Page 7

... Low Drive (High Impedance) Interleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 7/24 GS816018/32/36BT-250/200/150 = I SB A[1:0] A[1:0] A[1:0] A[1: © 2004, GSI Technology BPR 1999.05.18 ...

Page 8

... C D Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com may be used in any combination with BW to write single or multiple bytes. D 8/24 GS816018/32/36BT-250/200/150 B B Notes © 2004, GSI Technology ...

Page 9

... Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. State Diagram Key None X H None X L None Next CR X Next CR H Next CW X Next 9/24 GS816018/32/36BT-250/200/150 2 ADSP ADSC ADV © 2004, GSI Technology High-Z X High-Z X High ...

Page 10

... ADSP is tied high and ADV is tied low. Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 10/24 GS816018/32/36BT-250/200/150 First Read Burst Read BW, and GW © 2004, GSI Technology ...

Page 11

... Transitions shown in gray tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 11/24 GS816018/32/36BT-250/200/150 First Read Burst Read CR © 2004, GSI Technology ...

Page 12

... V maximum, with a pulse width not to exceed 50% tKC. DDn 12/24 GS816018/32/36BT-250/200/150 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 DDQ –0 +0.5 DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2004, GSI Technology Unit Notes ...

Page 13

... Min. Typ – +1.5 V maximum, with a pulse width not to exceed 50% tKC. DDn 13/24 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2004, GSI Technology ...

Page 14

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Overshoot Measurement and Timing Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 14/24 GS816018/32/36BT-250/200/150 50% tKC DD IL Typ. Max. Unit 30pF © 2004, GSI Technology ...

Page 15

... IN I Output Disable OUT –8 mA, V OH2 OH DDQ –8 mA, V OH3 OH DDQ 15/24 GS816018/32/36BT-250/200/150 Min – ≥ V – ≤ V –1 uA 100 uA IH ≥ V –100 uA IL ≤ V – – 2.375 V 1 3.135 V 2.4 V — © 2004, GSI Technology Max — — 0.4 V ...

Page 16

... GS816018/32/36BT-250/200/150 -250 -200 -150 –40 0 – 85°C 70°C 85°C 70°C 315 255 265 205 245 205 215 190 285 230 240 185 225 190 200 175 © 2004, GSI Technology –40 Unit to 85°C 215 mA 20 200 mA 15 195 mA 15 185 ...

Page 17

... GSI Technology ...

Page 18

... E2 and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 18/24 GS816018/32/36BT-250/200/150 Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2004, GSI Technology Deselect tKQX tHZ ...

Page 19

... Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 19/24 GS816018/32/36BT-250/200/150 Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2004, GSI Technology tKQX ...

Page 20

... Rev: 1.03 9/2005 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing tKH tKH tKC tKC tKL tKL tZZS tZZH 20/24 GS816018/32/36BT-250/200/150 2. The duration of SB tZZR © 2004, GSI Technology ...

Page 21

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. θ 0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 — 7° 21/24 GS816018/32/36BT-250/200/150 E1 E © 2004, GSI Technology ...

Page 22

... GS816036BT-250I 512K x 36 GS816036BT-200I 512K x 36 GS816036BT-150I GS816018BGT-250 GS816018BGT-200 GS816018BGT-150 512K x 32 GS816032BGT-250 512K x 32 GS816032BGT-200 512K x 32 GS816032BGT-150 512K x 36 GS816036BGT-250 512K x 36 GS816036BGT-200 512K x 36 GS816036BGT-150 GS816018BGT-250I GS816018BGT-200I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018BT-150IT. ...

Page 23

... Ordering Information for GSI Synchronous Burst RAMs (Continued) 1 Org Part Number GS816018BGT-150I 512K x 32 GS816032BGT-250I 512K x 32 GS816032BGT-200I 512K x 32 GS816032BGT-150I 512K x 36 GS816036BGT-250I 512K x 36 GS816036BGT-200I 512K x 36 GS816036BGT-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816018BT-150IT. ...

Page 24

... Creation of new datasheet • Updated overshoot/undershoot information Content • Added 300 MHz speed bin Content • Removed 300 MHz speed bin Content • Added Status column to Ordering Information table • Changed Pb-free to RoHS-compliant 24/24 GS816018/32/36BT-250/200/150 Page;Revisions;Reason © 2004, GSI Technology ...

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