LFXP2-8E-7FT256C Lattice, LFXP2-8E-7FT256C Datasheet - Page 235

• Manufacturer Part Number: LFXP2-8E-7FT256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-7FT256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
DDR registers of the complementary PIO are used in this mode. The complementary PIO register can no longer be
used to perform the DDR function. There are two clocks going to this primitive. The ECLK is connected to the faster
edge clock and the SCLK is connected to the slower FPGA clock. The DDR data output of this primitive is aligned
to the faster edge clock.
Figure 11-38 shows the primitive symbol for the ODDRX2B mode.
Figure 11-38. ODDRX2B Symbol
Table 11-10 lists the port names and descriptions for the ODDRX2B primitive.
Table 11-10. ODDRX2B Port Names
Figure 11-39 shows the LatticeXP2 Output Register Block in the ODDRX2B mode.
DA0, DB0
DA1, DB1
ECLK
SCLK
RST
Q
Port Name
I/O
O
I
I
I
I
I
Data at the negative edge of the clock
Data at the positive edge of the clock
This clock should be connected to the faster edge clock
This clock should be connected to the slower FPGA clock
Reset signal
DDR data output
ECLK
SCLK
DA0
DA1
DB0
DB1
RST
ODDRX2B
11-31
Description
Q
LatticeXP2 High-Speed I/O Interface