LFXP2-8E-7FT256C Lattice, LFXP2-8E-7FT256C Datasheet - Page 209

• Manufacturer Part Number: LFXP2-8E-7FT256C
• Description: FPGA - Field Programmable Gate Array 8K LUTs 201I/O Inst- on DSP 1.2V -7 Spd
• Manufacturer: Lattice

Specifications of LFXP2-8E-7FT256C

• Number Of Macrocells: 8000
• Number Of Programmable I/os: 201
• Data Ram Size: 226304
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FTBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
DQSDLL Configuration: By default, this DLL will generate a 90-degree phase shift for the DQS strobe based on
the frequency of the input reference clock to the DLL. The user can control the sensitivity to jitter by using the
LOCK_SENSITIVITY attribute. This configuration bit can be programmed to be either “HIGH” or “LOW”.
The DLL Lock Detect circuit has two modes of operation controlled by the LOCK_SENSITIVITY bit, which selects
more or less sensitivity to jitter. If this DLL is operated at or above 150 MHz, it is recommended that the
LOCK_SENSITIVITY bit be programmed “HIGH” (more sensitive). When running at or below 100 MHz, it is recom-
mended that the bit be programmed “LOW” (more tolerant). For 133 MHz, the LOCK_SENSITIVITY bit can go
either way.
DQSBUFC
This primitive implements the DQS delay and the DQS transition detector logic. Figure 11-7 shows the primitive
symbol.
Figure 11-7. DQSBUFC Symbol
The DQSBUFC is composed of the DQS Delay, the DQS Transition Detect and the DQSXFER block as shown in
Figure 11-8. This block inputs the DQS and delays it by 90 degrees. It also generates the DDR Clock Polarity and
the DQSXFER signal. The preamble detect (PRMBDET) signal is generated from the DQSI input using a voltage
divider circuit.
DQSI
CLK
READ
DQSDEL
XCLK
DQSBUFC
11-5
DDRCLKPOL
DATAVALID
PRMBDET
DQSXFER
DQSO
DQSC
LatticeXP2 High-Speed I/O Interface