LFXP6C-4TN144I Lattice, LFXP6C-4TN144I Datasheet - Page 370
LFXP6C-4TN144I
Manufacturer Part Number
LFXP6C-4TN144I
Description
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer
Lattice
Specifications of LFXP6C-4TN144I
Number Of Programmable I/os
100
Data Ram Size
73728
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
NCLK_DEL
ROUTE
Report:
From the Hold Report below, which was run for MIN conditions:
===============================================================
Preference: INPUT_SETUP PORT “ddr_dq_*” 2.000000 ns CLKNET “pll_nclk” ;
---------------------------------------------------------------------------------------------
---------------
Passed:
(to pll_nclk +)
Logical Details:
Constraint Details:
Physical Path Details:
Name
Source:
Data Path Delay:
Clock Path Delay:
Name
Destination:
•
•
•
-1.609ns INREG_HLD requirement (totaling -0.370ns) by 0.370ns
Feedback path:
t
t
t
0.000ns delay ddr_dq_31 to ddr_dq_31 plus
0.000ns hold offset ddr_dq_31 to clk (totaling 0.000ns) meets
3.144ns delay clk to ddr_dq_31 plus
1.905ns feedback compensation less
Data path ddr_dq_31 to ddr_dq_31:
PD
FDH
FPGA_CLK
= 0.0 ns
The following path meets requirements by 0.370ns
= -1.609 ns
Fanout
0.260ns is the minimum offset for this preference.
Fanout
---
136
32 items scored, 0 timing errors detected.
(min) = 3.144 - 1.905 = 1.239 ns
--------
--------
Cell type
Port
IO-FF In
Delay (ns)
0.385
2.886
3.271
Delay (ns)
0.000
0.000ns
3.144ns
LLHPPLL.CLKIN to
LLHPPLL.NCLK to
(11.8% logic, 88.2% route), 1 logic levels.
(0.0% logic, 0.0% route), 0 logic levels.
Pin type
Pad
Data in
(0.0% logic, 0.0% route), 0 logic levels.
(25.7% logic, 74.3% route), 2 logic levels.
Site
Site
18-10
Cell name
ddr_dq_31
U1_ddrct_np_o4_1_008/U3_databusif/ddr_dqoeZ0Z_31
LLHPPLL.NCLK U2_ddr_pll_orca/ddr_pll_0_0
LLHPPLL.FB pll_nclk
for the DDR SDRAM Controller IP Core
(clock net +/-)
Resource
Resource
Board Timing Guidelines
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