LFXP6C-4TN144I Lattice, LFXP6C-4TN144I Datasheet - Page 338
LFXP6C-4TN144I
Manufacturer Part Number
LFXP6C-4TN144I
Description
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer
Lattice
Specifications of LFXP6C-4TN144I
Number Of Programmable I/os
100
Data Ram Size
73728
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
The following are the HDL representations of the design in Figure 13-7.
The preferable way is to fully employ the PFU's natural “Ripple-mode”. A single PFU can support up to 8-bit ripple
functions with fast carry logic. Figure 13-8 is an example of 4-bit counter in PFU “Ripple Mode”. In Lattice Semicon-
ductor FPGA architectures, an internal generated clock can get on the clock spine for small skew clock distribution,
further enhancing the performance of the clock divider.
Figure 13-8. Use PFU “Ripple Mode”
Here are the HDL representations of the design in Figure 13-8.
-- VHDL Example of Daisy Chaining FF
...
-- 1st FF to divide Clock in half
CLK_DIV1: process(CLK, RST)
begin
end process CLK_DIV1;
-- 2nd FF to divide clock in half
CLK_DIV2: process(clk1, RST)
begin
end process CLK_DIV2;
-- VHDL : “RippleMode” Clock Divider
...
COUNT4: process(CLK, RST)
begin
end process COUNT4;
DIVBY4
DIVBY16 <= cnt(3);
if (RST='1') then
elsif (CLK'event and CLK='1') then
end if;
if (RST='1') then
elsif (clk1'event and clk1='1') then
end if;
if (RST='1') then
elsif (CLK'event and CLK='1') then
end if;
clk1 <= '0';
clk1 <= not clk1;
clk2 <= '0';
clk2 <= not clk2;
cnt <= (others=>'0');
cnt <= cnt + 1;
<= cnt(1);
Ripple Mode
Counter
LUT in
4-Bit
13-11
//Verilog : “RippleMode” Clock Divider
...
always @(posedge CLK or posedge RST)
begin
end
assign DIVBY4
assign DIVBY16 = cnt[3];
...
//Verilog Example of Daisy Chaining FF
...
always @(posedge CLK or posedge RST)
begin
end
always @(posedge clk1 or posedge RST)
begin
end
...
if (RST)
else
if (RST)
else
if (RST)
else
cnt = 4'b0;
cnt = cnt + 1'b1;
clk1 = 1'b0;
clk1 = !clk1;
clk2 = 1'b0;
clk2 = !clk2;
HDL Synthesis Coding Guidelines
for Lattice Semiconductor FPGAs
= cnt[1];
DIVBY2
DIVBY4
DIVBY8
DIVBY16
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