LFXP6C-4TN144I Lattice, LFXP6C-4TN144I Datasheet - Page 187
LFXP6C-4TN144I
Manufacturer Part Number
LFXP6C-4TN144I
Description
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer
Lattice
Specifications of LFXP6C-4TN144I
Number Of Programmable I/os
100
Data Ram Size
73728
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Pseudo Dual Port RAM (RAM_DP) – EBR-Based
The EBR blocks in the LatticeECP/EC and LatticeXP devices can be configured as Pseudo-Dual Port RAM or
RAM_DP. IPexpress allows users to generate the Verilog-HDL or VHDL along with an EDIF netlist for the memory
size as per design requirements.
IPexpress generates the memory module, as shown in Figure 9-23.
Figure 9-23. Pseudo Dual Port Memory Module Generated by IPexpress
The generated module makes use of these EBR blocks or primitives. For memory sizes smaller than an EBR block,
the module will be created in one EBR block. If the specified memory is larger than one EBR block, multiple EBR
block can be cascaded, in depth or width (as required to create these sizes).
The basic Pseudo Dual Port memory primitive for the LatticeECP/EC and LatticeXP devices is shown in Figure 9-
24.
Figure 9-24. Pseudo Dual Port RAM primitive or RAM_DP for LatticeECP/EC and LatticeXP Devices
In the Pseudo Dual Port RAM mode, the input data and address for the ports are registered at the input of the
memory array. The output data of the memory is optionally registered at the output.
The various ports and their definitions for the Single Port Memory are included in Table 9-7. The table lists the cor-
responding ports for the module generated by IPexpress and for the EBR RAM_DP primitive.
ADW[x:0]
WrAddress
WrClockEn
CS[2:0]
DI[y:0]
CLKW
WrClock
CEW
RST
WE
Reset
Data
WE
EBR based Pseudo
Dual Port Memory
RAM_DP
EBR
9-22
LatticeECP/EC and LatticeXP Devices
RdClock
RdClockEn
RdAddress
Q
ADR[x:0]
CLKR
CER
DO[y:0]
Memory Usage Guide
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