LFXP6C-4TN144I Lattice, LFXP6C-4TN144I Datasheet - Page 362
LFXP6C-4TN144I
Manufacturer Part Number
LFXP6C-4TN144I
Description
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer
Lattice
Specifications of LFXP6C-4TN144I
Number Of Programmable I/os
100
Data Ram Size
73728
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-144
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP6C-4TN144I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
- Current page: 362 of 397
- Download datasheet (10Mb)
Lattice Semiconductor
As shown in Figure 18-1, input to PLL is CLK (133MHz for DDR NP). The PLL generates pll_mclk (133MHz) and
pll_nclk (266MHz). The clocks ddr_clk and ddr_clk_n go to DDR memory and are delayed by I/O pad delay
with respect to pll_mclk. The clocks pll_mclk and pll_nclk are internal to the FPGA. Command and
address signals are clocked by a negative edge of pll_mclk. The signal dqs_out acts as a clock for DDR write
and is generated by negative edge of pll_nclk. The signal ddr_dq_out is the DDR write data bus and gener-
ated by positive edge of pll_nclk. The flops ddr_dq_* latch the read data and are clocked by positive edge of
pll_nclk.
Read Operation
Figure 18-2 shows the timing of the DDR read operation. Table 18-1 describes the timing arcs of the read opera-
tion.
Figure 18-2. Read Timing Diagram
flops (max case)
flops (min case)
(inside FPGA)
At DDR Interface
DQ at FPGA
DQ at FPGA
(max case )
DQ at DDR
DQ at DDR
(min case)
pll_mclk
Inside FPGA
ddr_clk
t
BDD
t
AC
+ t
(min )
PD
t
AC
(max)
t
BDD
18-2
+ t
PD
t
SKEW
for the DDR SDRAM Controller IP Core
t
BDD
Board Timing Guidelines
t
SKEW
t
+ t
AC
PD
(min )
t
AC
(max )
t
BDD
+ t
PD
Related parts for LFXP6C-4TN144I
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 188 I/O 1.8/2.5/3.3V -4 Spd
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 100 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -4 Spd
Manufacturer:
Lattice
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTs 142 IO 1.8 /2.5/3.3V -4 Spd I
Manufacturer:
Lattice
Part Number:
Description:
IC FPGA 5.8KLUTS 188I/O 256-BGA
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTS 142 I/O
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA - Field Programmable Gate Array 5.8K LUTS 100 I/O
Manufacturer:
Lattice
Datasheet:
Part Number:
Description:
FPGA, 1.8V FLASH, INSTANT ON, SMD
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 400MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 256-Pin FBGA Tray
Manufacturer:
LATTICE SEMICONDUCTOR
Datasheet:
Part Number:
Description:
FPGA LatticeXP Family 6000 Cells 360MHz 130nm (CMOS) Technology 1.8V/2.5V/3.3V 208-Pin PQFP Tray
Manufacturer:
Lattice
Datasheet: