LFEC3E-3QN208C Lattice, LFEC3E-3QN208C Datasheet - Page 47

• Manufacturer Part Number: LFEC3E-3QN208C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs
• Manufacturer: Lattice

Specifications of LFEC3E-3QN208C

• Number Of Macrocells: 3100
• Number Of Programmable I/os: 145
• Data Ram Size: 56320
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
RSDS
The LatticeECP/EC devices support differential RSDS standard. This standard is emulated using complementary
LVCMOS outputs in conjunction with a parallel resistor across the driver outputs. The RSDS input standard is sup-
ported by the LVDS differential input buffer. The scheme shown in Figure 3-4 is one possible solution for RSDS
standard implementation. Use LVDS25E mode with suggested resistors for RSDS operation. Resistor values in
Figure 3-4 are industry standard values for 1% resistors.
Figure 3-4. RSDS (Reduced Swing Differential Standard)
Table 3-4. RSDS DC Conditions
VCCIO = 2.5V
VCCIO = 2.5V
RSDS Buffer
Emulated
Z
R
R
R
V
V
V
V
Z
I
On-chip
DC
OUT
OH
OL
OD
BACK
S
P
T
CM
Parameter
Output impedance
Driver series resistor
Driver parallel resistor
Receiver termination
Output high voltage
Output low voltage
Output differential voltage
Output common mode voltage
Back impedance
DC output current
294
294
Description
121
3-11
Zo = 100
DC and Switching Characteristics
Typical
LatticeECP/EC Family Data Sheet
101.5
1.35
1.15
0.20
1.25
3.66
294
121
100
20
Off-chip
Units
100
ohm
ohm
ohm
ohm
ohm
mA
V
V
V
V
+
-