LFEC3E-3QN208C Lattice, LFEC3E-3QN208C Datasheet - Page 28

• Manufacturer Part Number: LFEC3E-3QN208C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTs
• Manufacturer: Lattice

Specifications of LFEC3E-3QN208C

• Number Of Macrocells: 3100
• Number Of Programmable I/os: 145
• Data Ram Size: 56320
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 100 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: PQFP-208
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-29. Output Register Block
Figure 2-30. ODDRXB Primitive
Tristate Register Block
The tristate register block provides the ability to register tri-state control signals from the core of the device before
they are passed to the sysI/O buffers. The block contains a register for SDR operation and an additional latch for
DDR operation. Figure 2-31 shows the diagram of the Tristate Register Block.
In SDR mode, ONEG1 feeds one of the flip-flops that then feeds the output. The flip-flop can be configured a D-
type or latch. In DDR mode, ONEG1 is fed into one register on the positive edge of the clock and OPOS1 is
latched. A multiplexer running off the same clock selects the correct register for feeding to the output (D0).
Routing
From
ONEG0
OPOS0
CLK1
*Latch is transparent when input is low.
CLK
LSR
DA
DB
/LATCH
D
D
D-Type
LE*
Latch
ODDRXB
2-25
Q
Q
Q
0
1
LatticeECP/EC Family Data Sheet
Programmed
Control
OUTDDN
0
1
To sysIO
Buffer
DO
Architecture