AGLP060V2-CSG289 Actel, AGLP060V2-CSG289 Datasheet - Page 27

• Manufacturer Part Number: AGLP060V2-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V2-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Sequential Cells Contribution—P
Combinatorial Cells Contribution—P
Routing Net Contribution—P
I/O Input Buffer Contribution—P
I/O Output Buffer Contribution—P
RAM Contribution—P
PLL Contribution—P
P
P
P
P
P
P
P
S-CELL
C-CELL
NET
INPUTS
OUTPUTS
MEMORY
PLL
F
N
P
N
multi-tile sequential cell is used, it should be accounted for as 1.
α
page
F
N
α
page
F
N
N
α
page
F
N
α
F
N
α
β
F
N
F
β
F
β
page
= P
F
= (N
CLK
AC1
CLK
CLK
CLK
CLK
CLK
READ-CLOCK
WRITE-CLOCK
CLKOUT
1
2
3
S-CELL
S-CELL
C-CELL
S-CELL
C-CELL
INPUTS
OUTPUTS
BLOCKS
1
1
1
2
2
= N
= N
= N
is the I/O buffer enable rate—guidelines are provided in
is the RAM enable rate for read operations.
DC4
is the RAM enable rate for write operations—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the I/O buffer toggle rate—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
is the toggle rate of VersaTile outputs—guidelines are provided in
S-CELL
= P
, P
= N
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
is the global clock signal frequency.
2-14.
2-14.
2-14.
2-14.
S-CELL
C-CELL
INPUTS
+ P
AC2
AC11
OUTPUTS
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as combinatorial modules in the design.
is the number of VersaTiles used as sequential modules in the design. When a
is the number of I/O input buffers used in the design.
is the output clock frequency.
is the number of RAM blocks used in the design.
AC13
is the number of I/O output buffers used in the design.
, P
+ N
*
* N
* (P
*
AC3
α
is the memory read clock frequency.
C-CELL
is the memory write clock frequency.
α
PLL
*F
BLOCKS
1
MEMORY
AC5
2
, and P
/ 2 * P
*
CLKOUT
/ 2 * P
α
+
) *
2
α
/ 2 *
AC7
* F
α
1
NET
AC9
AC4
1
/ 2 * P
READ-CLOCK
β
/ 2 * P
* F
INPUTS
* F
1
are device-dependent.
S-CELL
CLK
* P
OUTPUTS
CLK
AC6
AC8
AC10
C-CELL
R ev i si o n 1 1
) * F
* F
* F
*
CLK
1
CLK
β
CLK
2
+ P
AC12
* N
BLOCK
IGLOO PLUS Low Power Flash FPGAs
Table 2-19 on page
Table 2-19 on page
Table 2-20 on page
* F
WRITE-CLOCK
*
Table 2-19 on
Table 2-19 on
Table 2-19 on
β
Table 2-20 on
3
2-14.
2-14.
2-14.
2- 13