AGLP060V2-CSG289 Actel, AGLP060V2-CSG289 Datasheet - Page 10

• Manufacturer Part Number: AGLP060V2-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V2-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO PLUS Device Family Overview
*
Figure 1-1 • IGLOO PLUS Device Architecture Overview with Four I/O Banks (AGLP030, AGLP060, and
1- 4
Not supported by AGLP030 devices
Flash*Freeze Technology
The IGLOO PLUS device has an ultra-low power static mode, called Flash*Freeze mode, which retains
all SRAM and register information and can still quickly return to normal operation. Flash*Freeze
technology enables the user to quickly (within 1 µs) enter and exit Flash*Freeze mode by activating the
Flash*Freeze pin while all power supplies are kept at their original values. In addition, I/Os and global
I/Os can still be driven and can be toggling without impact on power consumption, clocks can still be
driven or can be toggling without impact on power consumption, and the device retains all core registers,
SRAM information, and I/O states. I/Os can be individually configured to either hold their previous state
or be tristated during Flash*Freeze mode. Alternatively, they can be set to a certain state using weak pull-
up or pull-down I/O attribute configuration. No power is consumed by the I/O banks, clocks, JTAG pins,
or PLL, and the device consumes as little as 5 µW in this mode.
Flash*Freeze technology allows the user to switch to Active mode on demand, thus simplifying the power
management of the device.
The Flash*Freeze pin (active low) can be routed internally to the core to allow the user's logic to decide
when it is safe to transition to this mode. Refer to
Flash*Freeze mode. It is also possible to use the Flash*Freeze pin as a regular I/O if Flash*Freeze mode
usage is not planned.
Figure 1-2 • IGLOO PLUS Flash*Freeze Mode
AGLP125)
Decryption*
ISP AES
User Nonvolatile
FlashRom
Mode Control
Flash*Freeze
Bank 0
Bank 2
Flash*Freeze
Technology
R ev isio n 1 1
Charge
Pumps
Flash*Freeze Pin
Figure 1-2
IGLOO PLUS
FPGA
Actel
for an illustration of entering/exiting
CCC
RAM Block
4,608-Bit Dual-Port
SRAM or FIFO Block*
I/Os
VersaTile
*