AGLP060V2-CSG289 Actel, AGLP060V2-CSG289 Datasheet - Page 25

• Manufacturer Part Number: AGLP060V2-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V2-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-16 • Different Components Contributing to the Static Power Consumption in IGLOO PLUS Devices
Table 2-17 • Different Components Contributing to Dynamic Power Consumption in IGLOO PLUS Devices
Parameter
PAC1
PAC2
PAC3
PAC4
PAC5
PAC6
PAC7
PAC8
PAC9
PAC10
PAC11
PAC12
PAC13
Parameter
PDC1
PDC2
PDC3
PDC4
PDC5
Notes:
1. This is the minimum contribution of the PLL when operating at lowest frequency.
2. For a different output load, drive strength, or slew rate, Actel recommends using the Actel power spreadsheet calculator
or the SmartPower tool in Actel Libero
For IGLOO PLUS V2 or V5 Devices, 1.5 V Core Supply Voltage
For IGLOO PLUS V2 Devices, 1.2 V Core Supply Voltage
Clock contribution of a Global Rib
Clock contribution of a Global Spine
Clock contribution of a VersaTile row
Clock contribution of a VersaTile used as a sequential module
First contribution of a VersaTile used as a sequential module
Second contribution of a VersaTile used as a sequential module
Contribution of a VersaTile used as a combinatorial module
Average contribution of a routing net
Contribution of an I/O input pin (standard-dependent)
Contribution of an I/O output pin (standard-dependent)
Average contribution of a RAM block during a read operation
Average contribution of a RAM block during a write operation
Dynamic contribution for PLL
Array static power in Active mode
Array static power in Static (Idle) mode
Array static power in Flash*Freeze mode
Static PLL contribution
Bank quiescent power (VCCI-dependent)
Definition
®
Integrated Design Environment (IDE) software.
Definition
R ev i si o n 1 1
AGLP125
Device-Specific Static Power (mW)
See
See
See
See
IGLOO PLUS Low Power Flash FPGAs
Device-Specific Dynamic Power
AGLP125 AGLP060 AGLP030
Table 2-12 on page 2-8
Table 2-12 on page 2-8
Table 2-11 on page 2-8
Table 2-9 on page 2-7
7.07
0.52
See
See
AGLP060
Table 2-13 on page 2-9
Table 2-14 on page 2-9
1.84
(µW/MHz)
1
0.045
0.186
25.00
30.00
0.52
0.07
0.11
0.45
2.10
5.96
0.52
AGLP030
5.96
0.26
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