AGLP060V2-CSG289 Actel, AGLP060V2-CSG289 Datasheet - Page 12

• Manufacturer Part Number: AGLP060V2-CSG289
• Description: FPGA - Field Programmable Gate Array 60K System Gates
• Manufacturer: Actel

Specifications of AGLP060V2-CSG289

• Processor Series: AGLP060
• Core: IP Core
• Number Of Macrocells: 512
• Maximum Operating Frequency: 250 MHz
• Number Of Programmable I/os: 4
• Data Ram Size: 4608 bit
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AGLP-Eval-Kit, AGL-Dev-Kit-SCS, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA, Flashpro 4, Flashpro 3, Flashpro Lite
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Number Of Gates: 60 K
• Package / Case: CSP-289
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

IGLOO PLUS Device Family Overview
1- 6
SRAM and FIFO
IGLOO PLUS devices (except AGLP030 devices) have embedded SRAM blocks along their north side.
Each variable-aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are
256×18, 512×9, 1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports
that can be configured with different bit widths on each port. For example, data can be sent through a
4-bit port and read as a single bitstream. The embedded SRAM blocks can be initialized via the device
JTAG port (ROM emulation mode) using the UJTAG macro (except in AGLP030 devices).
In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM
block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width
and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and
Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control
unit contains the counters necessary for generation of the read and write address pointers. The
embedded SRAM/FIFO blocks can be cascaded to create larger configurations.
PLL and CCC
IGLOO PLUS devices provide designers with very flexible clock conditioning circuit (CCC) capabilities.
Each member of the IGLOO PLUS family contains six CCCs. One CCC (center west side) has a PLL.
The AGLP030 device does not have a PLL or CCCs; it contains only inputs to six globals.
The six CCC blocks are located at the four corners and the centers of the east and west sides. One CCC
(center west side) has a PLL.
The four corner CCCs and the east CCC allow simple clock delay operations as well as clock spine
access.
The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs
located near the CCC that have dedicated connections to the CCC block.
The CCC block has these key features:
Additional CCC specifications:
Global Clocking
IGLOO PLUS devices have extensive support for multiple clocking domains. In addition to the CCC and
PLL support described above, there is a comprehensive global clock distribution network.
Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant
global networks. The VersaNets can be driven by the CCC or directly accessed from the core via
multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid
distribution of high-fanout nets.
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Wide input frequency range (f
Output frequency range (f
2 programmable delay types for clock skew minimization
Clock frequency synthesis (for PLL only)
Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider
configuration (for PLL only).
Output duty cycle = 50% ± 1.5% or better (for PLL only)
Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global
network used (for PLL only)
Maximum acquisition time is 300 µs (for PLL only)
Exceptional tolerance to input period jitter—allowable input jitter is up to 1.5 ns (for PLL only)
Four precise phases; maximum misalignment between adjacent phases (for PLL only) is 40 ps ×
250 MHz / f
OUT_CCC
OUT_CCC
IN_CCC
) = 0.75 MHz up to 250 MHz
) = 1.5 MHz up to 250 MHz
R ev isio n 1 1