A40MX04-PLG44 Actel, A40MX04-PLG44 Datasheet - Page 79
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A40MX04-PLG44
Manufacturer Part Number
A40MX04-PLG44
Description
FPGA - Field Programmable Gate Array 6K System Gates
Manufacturer
Actel
Datasheet
1.A40MX04-PLG44.pdf
(124 pages)
Specifications of A40MX04-PLG44
Processor Series
A40MX04
Core
IP Core
Number Of Macrocells
547
Maximum Operating Frequency
250 MHz
Number Of Programmable I/os
69
Delay Time
5.6 ns
Supply Voltage (max)
5.5 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
3 V
Number Of Gates
6000
Package / Case
PLCC-44
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
A40MX04-PLG44I
Manufacturer:
Microsemi SoC
Quantity:
10 000
Table 39 •
Parameter Description
Logic Module Combinatorial Functions
t
t
Logic Module Predicted Routing Delays
t
t
t
t
t
t
Logic Module Sequential Timing
t
t
t
t
t
t
t
t
t
Synchronous SRAM Operations
t
t
t
t
t
Notes:
1. For dual-module macros, use t
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
4. Set-up and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/
5. Delays based on 35 pF loading.
PD
PDD
RD1
RD2
RD3
RD4
RD5
RDD
CO
GO
SUD
HD
RO
SUENA
HENA
WCLKA
WASYN
RC
WC
RCKHL
RCO
ADSU
device performance. Post-route timing analysis or simulation is required to determine actual performance.
obtained from the Timer utility.
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
A42MX36 Timing Characteristics (Nominal 3.3V Operation)
(Worst-Case Commercial Conditions, V
Internal Array Module Delay
Internal Decode Module Delay
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Decode-to-Output Routing Delay
Flip-Flop Clock-to-Output
Latch Gate-to-Output
Flip-Flop (Latch) Set-Up Time
Flip-Flop (Latch) Hold Time
Flip-Flop (Latch) Reset-to-Output
Flip-Flop (Latch) Enable Set-Up
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active
Pulse Width
Flip-Flop (Latch) Asynchronous
Pulse Width
Read Cycle Time
Write Cycle Time
Clock HIGH/LOW Time
Data Valid After Clock HIGH/LOW
Address/Data Set-Up Time
PD1
+ t
3, 4
RD1
+ t
1
2
PDn
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
‘–3’ Speed
0.4
0.0
1.0
0.0
4.6
6.1
9.5
9.5
4.8
2.3
, t
CO
CCA
+ t
1.9
2.2
1.3
1.8
2.3
2.8
4.6
0.5
1.8
1.8
2.2
4.8
RD1
= 3.0V, T
+ t
v6.1
10.5
10.5
‘–2’ Speed
PDn
0.5
0.0
1.1
0.0
5.2
6.8
5.3
2.5
, or t
J
= 70°C)
0.5
5.3
PD1
2.1
2.5
1.5
2.0
2.5
3.1
5.2
2.0
2.0
2.4
+ t
RD1
11.9
11.9
‘–1’ Speed
0.6
0.0
1.2
0.0
5.8
7.7
6.0
2.8
+ t
SUD
2.8
1.7
2.3
2.8
3.5
5.8
0.6
2.3
6.0
2.3
2.3
2.7
, whichever is appropriate.
‘Std’ Speed
14.0
14.0
0.7
0.0
1.4
0.0
6.9
9.0
7.0
3.4
40MX and 42MX FPGA Families
2.7
3.3
2.0
2.7
3.4
4.1
6.9
0.7
2.7
2.7
3.2
7.0
12.6
19.6
19.6
‘–F’ Speed
0.9
0.0
2.0
0.0
9.6
9.8
4.8
3.8
4.7
2.7
3.7
4.7
5.7
9.6
1.0
3.7
3.7
4.5
9.8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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